| 1995 |
|---|
| 24 | EE | Shigeru Yamashita,
Yahiko Kambayashi,
Saburo Muroga:
Optimization methods for lookup-table-based FPGAs using transduction method.
ASP-DAC 1995 |
| 1993 |
|---|
| 23 | | Chieng-Fai Lim,
Prithviraj Banerjee,
Kaushik De,
Saburo Muroga:
A Shared Memory Parallel Algorithm for Logic Synthesis.
VLSI Design 1993: 317-322 |
| 1991 |
|---|
| 22 | EE | Kuang-Chien Chen,
Yusuke Matsunaga,
Saburo Muroga,
Masahiro Fujita:
A Resynthesis Approach for Network Optimization.
DAC 1991: 458-463 |
| 21 | EE | Johnson Chan Limqueco,
Saburo Muroga:
Logic Optimization of MOS Networks.
DAC 1991: 464-469 |
| 20 | | Saburo Muroga:
Computer-Aided Logic Synthesis for VLSI Chips.
Advances in Computers 32: 1-103 (1991) |
| 19 | | Sung Je Hong,
Saburo Muroga:
Absolute Minimization of Completely Specified Switching Functions.
IEEE Trans. Computers 40(1): 53-65 (1991) |
| 1990 |
|---|
| 18 | EE | Kuang-Chien Chen,
Saburo Muroga:
Timing Optimization for Multi-Level Combinational Networks.
DAC 1990: 339-344 |
| 1989 |
|---|
| 17 | | Saburo Muroga,
Yahiko Kambayashi,
Hung Chi Lai,
Jay Niel Culliney:
The Transduction Method-Design of Logic Networks Based on Permissible Functions.
IEEE Trans. Computers 38(10): 1404-1424 (1989) |
| 1988 |
|---|
| 16 | EE | Hung Chi Lai,
Saburo Muroga:
Design of MOS networks in single-rail input logic for incompletely specified functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 339-345 (1988) |
| 1987 |
|---|
| 15 | | Hung Chi Lai,
Saburo Muroga:
Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables.
IEEE Trans. Computers 36(2): 157-166 (1987) |
| 14 | | Robert Brian Cutler,
Saburo Muroga:
Derivation of Minimal Sums for Completely Specified Functions.
IEEE Trans. Computers 36(3): 277-292 (1987) |
| 1986 |
|---|
| 13 | | Yahiko Kambayashi,
Saburo Muroga:
Properties of Wired Logic.
IEEE Trans. Computers 35(6): 550-563 (1986) |
| 1985 |
|---|
| 12 | | Ming Huei Young,
Saburo Muroga:
Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables.
IEEE Trans. Computers 34(6): 523-541 (1985) |
| 1983 |
|---|
| 11 | | Akito Sakurai,
Saburo Muroga:
Parallel Binary Adders with a Minimum Number of Connections.
IEEE Trans. Computers 32(10): 969-976 (1983) |
| 1982 |
|---|
| 10 | | Hung Chi Lai,
Saburo Muroga:
Logic Networks of Carry-Save Adders.
IEEE Trans. Computers 31(9): 870-882 (1982) |
| 1979 |
|---|
| 9 | | Jay Niel Culliney,
Ming Huei Young,
T. Nakagawa,
Saburo Muroga:
Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions.
IEEE Trans. Computers 28(1): 76-85 (1979) |
| 8 | | Robert Brian Cutler,
Saburo Muroga:
Comments on ``Computing Irredundant Normal Forms from Abbreviated Presence Functions''.
IEEE Trans. Computers 28(11): 874-875 (1979) |
| 7 | | Robert Brian Cutler,
Saburo Muroga:
Comments on ``Generalization of Consensus Theory and Application to the Minimization of Boolean Functions''.
IEEE Trans. Computers 28(7): 542-543 (1979) |
| 6 | | Hung Chi Lai,
Saburo Muroga:
Minimum Parallel Binary Adders with NOR (NAND) Gates.
IEEE Trans. Computers 28(9): 648-659 (1979) |
| 1976 |
|---|
| 5 | | Saburo Muroga,
Hung Chi Lai:
Minimization of Logic Networks Under a Generalized Cost Function.
IEEE Trans. Computers 25(9): 893-907 (1976) |
| 1962 |
|---|
| 4 | | Saburo Muroga:
Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight
FOCS 1962: 169-184 |
| 1961 |
|---|
| 3 | | Calvin C. Elgot,
Saburo Muroga:
Two problems on threshold functions
FOCS 1961: 166 |
| 2 | | Saburo Muroga:
Functional forms of majority functions and a necessary and sufficient condition for their realizability
FOCS 1961: 39-46 |
| 1959 |
|---|
| 1 | | Saburo Muroga:
The principle of majority decision logical elements and the complexity of their circuits.
IFIP Congress 1959: 400-406 |
