| 2008 |
|---|
| 10 | EE | Shi-Hao Chen,
Jiing-Yuan Lin:
Experiences of low power design implementation and verification.
ASP-DAC 2008: 742-747 |
| 2007 |
|---|
| 9 | EE | Shi-Hao Chen,
Ke-Cheng Chu,
Jiing-Yuan Lin,
Cheng-Hong Tsai:
DFM/DFY practices during physical designs for timing, signal integrity, and power.
ASP-DAC 2007: 232-237 |
| 8 | EE | Chien-Liang Chen,
Jiing-Yuan Lin,
Youn-Long Lin:
Integration, Verification and Layout of a Complex Multimedia SOC
CoRR abs/0710.4667: (2007) |
| 2005 |
|---|
| 7 | EE | Chien-Liang Chen,
Jiing-Yuan Lin,
Youn-Long Lin:
Integration, Verification and Layout of a Complex Multimedia SOC.
DATE 2005: 1116-1117 |
| 2000 |
|---|
| 6 | EE | Heng-Liang Huang,
Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A new method for constructing IP level power model based on power sensitivity.
ASP-DAC 2000: 135-140 |
| 1999 |
|---|
| 5 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A structure-oriented power modeling technique for macrocells.
IEEE Trans. VLSI Syst. 7(3): 380-391 (1999) |
| 1997 |
|---|
| 4 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A power modeling and characterization method for macrocells using structure information.
ICCAD 1997: 502-506 |
| 1996 |
|---|
| 3 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A power modeling and characterization method for the CMOS standard cell library.
ICCAD 1996: 400-404 |
| 1995 |
|---|
| 2 | EE | Wen-Zen Shen,
Jiing-Yuan Lin,
Fong-Wen Wang:
Transistor reordering rules for power reduction in CMOS gates.
ASP-DAC 1995 |
| 1994 |
|---|
| 1 | EE | Jiing-Yuan Lin,
Tai-Chien Liu,
Wen-Zen Shen:
A cell-based power estimation in CMOS combinational circuits.
ICCAD 1994: 304-309 |
