Jessica Qian

List of publications from the DBLP Bibliography Server - FAQ

1994

2 EE Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage: A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580

1 EE Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage: Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1526-1535 (1994)

1994
2	EE	Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage: A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580
1	EE	Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage: Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1526-1535 (1994)

Coauthor Index

1	Florentin Dartu	[2]
2	Noel Menezes	[2]
3	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[1] [2]
4	Satyamurthy Pullela	[1]