1. PACS 2000: Cambridge, MA, USA

@proceedings{DBLP:conf/pacs/2000,
  editor    = {Babak Falsafi and
               T. N. Vijaykumar},
  title     = {Power-Aware Computer Systems, First International Workshop, PACS
               2000, Cambridge, MA, USA, November 12, 2000, Revised Papers},
  booktitle = {PACS},
  publisher = {Springer},
  series    = {Lecture Notes in Computer Science},
  volume    = {2008},
  year      = {2001},
  isbn      = {3-540-42329-X},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Power-Aware Microarchitectural/Circuit Techniques

• Flavius Gruian:
  System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors. 1-12
  Electronic Edition (Springer LINK) BibTeX
• Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He:
  Ramp Up/Down Functional Unit to Reduce Step Power. 13-24
  Electronic Edition (Springer LINK) BibTeX
• Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi:
  An Adaptive Issue Queue for Reduced Power at High Performance. 25-39
  Electronic Edition (Springer LINK) BibTeX

Application/Compiler Optimizations

• Paul Marchal, Chun Wong, Aggeliki S. Prayati, Nathalie Cossement, Francky Catthoor, Rudy Lauwereins, Diederik Verkest, Hugo De Man:
  Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform. 40-50
  Electronic Edition (Springer LINK) BibTeX
• Jeongseon Euh, Wayne Burleson:
  Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering. 51-64
  Electronic Edition (Springer LINK) BibTeX
• Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao:
  Compiler-Directed Dynamic Frequency and Voltage Scheduling. 65-81
  Electronic Edition (Springer LINK) BibTeX

Exploiting IPC/Memory Slack

• Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan:
  Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power. 82-96
  Electronic Edition (Springer LINK) BibTeX
• Roberto Maro, Yu Bai, R. Iris Bahar:
  Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. 97-111
  Electronic Edition (Springer LINK) BibTeX

Power/Performance Models and Tools

• Ashutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch:
  TEM²P²EST: A Thermal Enabled Multi-model Power/Performance ESTimator. 112-125
  Electronic Edition (Springer LINK) BibTeX
• David Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose:
  Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor. 126-136
  Electronic Edition (Springer LINK) BibTeX
• Soraya Ghiasi, Dirk Grunwald:
  A Comparison of Two Architectural Power Models. 137-152
  Electronic Edition (Springer LINK) BibTeX