| 2002 |
|---|
| 9 | EE | Shuo Sheng,
Koichiro Takayama,
Michael S. Hsiao:
Effective safety property checking using simulation-based sequential ATPG.
DAC 2002: 813-818 |
| 8 | | Rajarshi Mukherjee,
Jawahar Jain,
Koichiro Takayama,
Jacob A. Abraham,
Donald S. Fussell,
Masahiro Fujita:
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table.
Formal Methods in System Design 21(1): 95-101 (2002) |
| 2001 |
|---|
| 7 | | Farzan Fallah,
Koichiro Takayama:
A New Functional Test Program Generation Methodology.
ICCD 2001: 76-81 |
| 6 | EE | Subramanian Rajagopalan,
Sreeranga P. Rajan,
Sharad Malik,
Sandro Rigo,
Guido Araujo,
Koichiro Takayama:
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1319-1328 (2001) |
| 2000 |
|---|
| 5 | EE | Rajarshi Mukherjee,
Jawahar Jain,
Koichiro Takayama,
Masahiro Fujita:
Automatic partitioning for efficient combinatorial verification.
ASP-DAC 2000: 67-72 |
| 1999 |
|---|
| 4 | EE | Vamsi Boppana,
Sreeranga P. Rajan,
Koichiro Takayama,
Masahiro Fujita:
Model Checking Based on Sequential ATPG.
CAV 1999: 418-430 |
| 3 | EE | Rajarshi Mukherjee,
Jawahar Jain,
Koichiro Takayama,
Masahiro Fujita,
Jacob A. Abraham,
Donald S. Fussell:
An Efficient Filter-Based Approach for Combinational Verification.
DATE 1999: 132-137 |
| 2 | EE | Rajarshi Mukherjee,
Jawahar Jain,
Koichiro Takayama,
Masahiro Fujita,
Jacob A. Abraham,
Donald S. Fussell:
An efficient filter-based approach for combinational verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1542-1557 (1999) |
| 1988 |
|---|
| 1 | | Fumiyasu Hirose,
Koichiro Takayama,
Nobuaki Kawato:
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator.
ITC 1988: 102-107 |
