2009 |
12 | EE | Yann Oddos,
Katell Morin-Allory,
Dominique Borrione,
Marc Boule,
Zeljko Zilic:
MYGEN: automata-based on-line test generator for assertion-based verification.
ACM Great Lakes Symposium on VLSI 2009: 75-80 |
2008 |
11 | EE | Yann Oddos,
Katell Morin-Allory,
Dominique Borrione:
Assertion-Based Design with Horus.
MEMOCODE 2008: 75-76 |
2007 |
10 | | Yann Oddos,
Katell Morin-Allory,
Dominique Borrione:
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties.
DDECS 2007: 383-388 |
9 | EE | Katell Morin-Allory,
Laurent Fesquet,
Benjamin Roustan,
Dominique Borrione:
Asynchronous online-monitoring of logical and temporal assertions.
FDL 2007: 286-290 |
8 | EE | Katell Morin-Allory,
Eric Gascard,
Dominique Borrione:
Synthesis of Property Monitors for Online Fault Detection.
Journal of Circuits, Systems, and Computers 16(6): 943-960 (2007) |
2006 |
7 | EE | Katell Morin-Allory,
Dominique Borrione:
Proven correct monitors from PSL specifications.
DATE 2006: 1246-1251 |
6 | EE | Katell Morin-Allory,
Dominique Borrione:
On-line Monitoring of Properties Built on Regular Expressions.
FDL 2006: 249-255 |
5 | EE | Katell Morin-Allory,
Laurent Fesquet,
Dominique Borrione:
Asynchronous Assertion Monitors for multi-Clock Domain System Verification.
IEEE International Workshop on Rapid System Prototyping 2006: 98-102 |
4 | EE | Yann Oddos,
Katell Morin-Allory,
Dominique Borrione:
On-Line Test Vector Generation from Temporal Constraints Written in PSL.
VLSI-SoC 2006: 397-402 |
2005 |
3 | EE | Katell Morin-Allory,
David Cachera:
Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic.
CHARME 2005: 376-379 |
2 | EE | David Cachera,
Katell Morin-Allory:
Verification of safety properties for parameterized regular systems.
ACM Trans. Embedded Comput. Syst. 4(2): 228-266 (2005) |
2003 |
1 | EE | David Cachera,
Katell Morin-Allory:
Verification of Control Properties in the Polyhedral Model.
MEMOCODE 2003: 265- |