| 2008 |
|---|
| 9 | EE | Sumanta Chaudhuri,
Sylvain Guilley,
Philippe Hoogvorst,
Jean-Luc Danger,
Taha Beyrouthy,
Alin Razafindraibe,
Laurent Fesquet,
Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage.
ARC 2008: 87-98 |
| 2007 |
|---|
| 8 | EE | Alin Razafindraibe,
Michel Robert,
Philippe Maurine:
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA.
PATMOS 2007: 340-351 |
| 7 | EE | Alin Razafindraibe,
Philippe Maurine:
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates.
PATMOS 2007: 394-403 |
| 6 | | Philippe Hoogvorst,
Sylvain Guilley,
Sumanta Chaudhuri,
Alin Razafindraibe,
Taha Beyrouthy,
Laurent Fesquet:
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.
ReCoSoC 2007: 15-22 |
| 5 | EE | Alin Razafindraibe,
Michel Robert,
Philippe Maurine:
Improvement of dual rail logic as a countermeasure against DPA.
VLSI-SoC 2007: 270-275 |
| 2006 |
|---|
| 4 | EE | Alin Razafindraibe,
Michel Robert,
Philippe Maurine:
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks.
PATMOS 2006: 634-644 |
| 3 | EE | Alin Razafindraibe,
Philippe Maurine,
Michel Robert,
Marc Renaudin:
Security evaluation of dual rail logic against DPA attacks.
VLSI-SoC 2006: 181-186 |
| 2005 |
|---|
| 2 | EE | Alin Razafindraibe,
Michel Robert,
Marc Renaudin,
Philippe Maurine:
A Method to Design Compact Dual-rail Asynchronous Primitives.
PATMOS 2005: 571-580 |
| 1 | EE | Alin Razafindraibe,
Michel Robert,
Philippe Maurine:
Compact and Secured Primitives for the Design of Asynchronous Circuits.
J. Low Power Electronics 1(1): 20-26 (2005) |
