| 2008 |
|---|
| 5 | EE | Yuichiro Murachi,
Kusuke Mizuno,
Junichi Miyakoshi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Fang Yin,
Jangchung Lee,
Tetsuya Kamino,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.
ISCAS 2008: 848-851 |
| 4 | EE | Yuichiro Murachi,
Junichi Miyakoshi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Fang Yin,
Jangchung Lee,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.
IEICE Transactions 91-C(4): 465-478 (2008) |
| 2006 |
|---|
| 3 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masahiko Yoshimoto,
Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
VLSI-SoC 2006: 192-197 |
| 2 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Tetsuro Matsuno,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masayuki Miyama,
Masahiko Yoshimoto:
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
IEICE Transactions 89-A(12): 3623-3633 (2006) |
| 1 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.
IEICE Transactions 89-C(11): 1629-1636 (2006) |
