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Tetsuro Matsuno

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2006
4EEJunichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno: A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC 2006: 192-197
3EEJunichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto: A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Transactions 89-A(12): 3623-3633 (2006)
2005
2EEYuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto: A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. IEICE Transactions 88-A(12): 3492-3499 (2005)
1EEJunichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto: A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. IEICE Transactions 88-C(4): 559-569 (2005)

Coauthor Index

1Masaki Hamamoto [3] [4]
2Koji Hamano [1] [2]
3Takahiro Iinuma [3] [4]
4Tomokazu Ishihara [3] [4]
5Hiroshi Kawaguchi [3] [4]
6Junichi Miyakoshi [1] [2] [3] [4]
7Masayuki Miyama [1] [2] [3]
8Yuichiro Murachi [1] [2] [3] [4]
9Masahiko Yoshimoto [1] [2] [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)