| 2006 |
|---|
| 4 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masahiko Yoshimoto,
Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
VLSI-SoC 2006: 192-197 |
| 3 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Tetsuro Matsuno,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masayuki Miyama,
Masahiko Yoshimoto:
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
IEICE Transactions 89-A(12): 3623-3633 (2006) |
| 2005 |
|---|
| 2 | EE | Yuichiro Murachi,
Koji Hamano,
Tetsuro Matsuno,
Junichi Miyakoshi,
Masayuki Miyama,
Masahiko Yoshimoto:
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.
IEICE Transactions 88-A(12): 3492-3499 (2005) |
| 1 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Koji Hamano,
Tetsuro Matsuno,
Masayuki Miyama,
Masahiko Yoshimoto:
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation.
IEICE Transactions 88-C(4): 559-569 (2005) |
