2009 | ||
---|---|---|
49 | EE | Pradeep Rao, Kazuaki Murakami: Empirical Performance Models for Java Workloads. ARCS 2009: 219-232 |
2008 | ||
48 | EE | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690 |
47 | EE | Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. ISLPED 2008: 241-246 |
46 | EE | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. ISVLSI 2008: 363-368 |
45 | EE | Ryutaro Susukita, Hisashige Ando, Mutsumi Aoyagi, Hiroaki Honda, Yuichi Inadomi, Koji Inoue, Shigeru Ishizuki, Yasunori Kimura, Hidemi Komatsu, Motoyoshi Kurokawa, Kazuaki Murakami, Hidetomo Shibamura, Shuji Yamamura, Yunqing Yu: Performance prediction of large-scale parallell system and application using macro-level simulation. SC 2008: 20 |
44 | EE | Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki Murakami: Performance Models for MPI Collective Communications with Network Contention. IEICE Transactions 91-B(4): 1015-1024 (2008) |
43 | EE | Naofumi Takagi, Kazuaki Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda: Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits. IEICE Transactions 91-C(3): 350-355 (2008) |
42 | EE | Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Transactions 91-C(4): 410-417 (2008) |
41 | EE | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems. IEICE Transactions 91-C(4): 418-431 (2008) |
40 | EE | Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions. IEICE Transactions 91-C(4): 497-508 (2008) |
39 | EE | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: An architecture framework for an adaptive extensible processor. The Journal of Supercomputing 45(3): 313-340 (2008) |
2007 | ||
38 | EE | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: The effect of temperature on cache size tuning for low energy embedded systems. ACM Great Lakes Symposium on VLSI 2007: 453-456 |
37 | EE | Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Task scheduling for reliable cache architectures of multiprocessor systems. DATE 2007: 1490-1495 |
36 | EE | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi: Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. DATE 2007: 325-330 |
35 | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. ESA 2007: 169-176 | |
34 | EE | Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260 |
33 | EE | Takesi Soga, Kouji Kurihara, Takeshi Nanri, Motoyoshi Kurokawa, Kazuaki Murakami: Dynamic Optimization of Load Balance in MPI Broadcast. PVM/MPI 2007: 387-388 |
32 | EE | Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki Murakami, Guilherme de Melo Baptista Domingues: Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms. SBAC-PAD 2007: 203-210 |
31 | EE | Mariko Sakamoto, Akira Katsuno, Go Sugizaki, Toshio Yoshida, Aiichiro Inoue, Koji Inoue, Kazuaki Murakami: A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips. IEICE Transactions 90-C(10): 1972-1982 (2007) |
30 | EE | Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Transactions 90-C(10): 1983-1991 (2007) |
29 | EE | Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki Murakami: Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Transactions 90-C(5): 1012-1020 (2007) |
28 | EE | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Transactions 90-D(12): 1956-1966 (2007) |
2006 | ||
27 | EE | Koji Hashimoto, Vasily G. Moshnyaga, Kazuaki Murakami: Circuit Area-latency Optimization Technique for High-precision Elementary Functions. APCCAS 2006: 1406-1409 |
26 | EE | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue: An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230 |
25 | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori: GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA 2006: 227-230 | |
24 | EE | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi: Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731 |
23 | EE | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4 |
22 | EE | Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki Murakami: Collective Communication Costs Analysis over Gigabit Ethernet and InfiniBand. HiPC 2006: 547-559 |
21 | EE | Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami: Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS 2006 |
20 | EE | Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura: A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006 |
19 | EE | Hamid Noori, Kazuaki Murakami: Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications. SAC 2006: 937-938 |
18 | EE | Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki Murakami: REDEFIS: a system with a redefinable instruction set processor. SBCCI 2006: 14-19 |
17 | EE | Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura: Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Transactions 89-C(3): 377-383 (2006) |
2005 | ||
16 | EE | Reiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. IEICE Transactions 88-A(4): 862-868 (2005) |
2004 | ||
15 | EE | Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga: Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI 2004: 179-186 |
2002 | ||
14 | EE | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Reducing power consumption of instruction ROMs by exploiting instruction frequency. APCCAS (2) 2002: 1-6 |
13 | EE | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A Low Energy Set-Associative I-Cache with Extended BTB. ICCD 2002: 187- |
12 | EE | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A history-based I-cache for low-energy multimedia applications. ISLPED 2002: 148-153 |
11 | EE | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. PACS 2002: 18-32 |
2001 | ||
10 | EE | Takanori Okuma, Koji Hashimoto, Kazuaki Murakami: Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication. ASP-DAC 2001: 37-38 |
2000 | ||
9 | EE | Koji Inoue, Koji Kai, Kazuaki Murakami: Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. Intelligent Memory Systems 2000: 169-178 |
1999 | ||
8 | EE | Koji Inoue, Koji Kai, Kazuaki Murakami: Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. HPCA 1999: 218-222 |
7 | EE | Koji Inoue, Tohru Ishihara, Kazuaki Murakami: Way-predicting set-associative cache for high performance and low energy consumption. ISLPED 1999: 273-275 |
1998 | ||
6 | EE | Taku Ohsawa, Koji Kai, Kazuaki Murakami: Optimizing the DRAM refresh count for merged DRAM/logic LSIs. ISLPED 1998: 82-87 |
1993 | ||
5 | EE | Takashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura: A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing 1993: 308-317 |
1992 | ||
4 | EE | Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita: Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. ICS 1992: 272-281 |
1989 | ||
3 | EE | Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita: The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. ICS 1989: 351-360 |
2 | Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita: The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture. IFIP Congress 1989: 995-1000 | |
1 | EE | Kazuaki Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita: SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ISCA 1989: 78-85 |