2006 | ||
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2 | S. Biswas, S. Mukhopadhyay, P. Patra, D. Sarkar: Concurrent Testing of Digital Circuits for Advanced Fault Models. DDECS 2006: 204-209 | |
2002 | ||
1 | EE | B. Chappell, X. Wang, P. Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain: A System-Level Solution to Domino Synthesis with 2 GHz Application. ICCD 2002: 164- |
1 | S. Biswas | [2] |
2 | B. Chappell | [1] |
3 | W. Gomes | [1] |
4 | Satyanarayan Gupta | [1] |
5 | S. Hussain | [1] |
6 | S. Jain | [1] |
7 | H. Krishnamurthy | [1] |
8 | S. Mukhopadhyay | [2] |
9 | D. Sarkar | [2] |
10 | Prashant Saxena | [1] |
11 | S. Varadarajan | [1] |
12 | J. Vendrell | [1] |
13 | M. Venkateshmurthy | [1] |
14 | X. Wang | [1] |