Koji Inoue

2008
35	EE	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690
34	EE	Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue: Improved Policies for Drowsy Caches in Embedded Processors. DELTA 2008: 362-367
33	EE	Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. ISLPED 2008: 241-246
32	EE	Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. ISVLSI 2008: 363-368
31	EE	Ryutaro Susukita, Hisashige Ando, Mutsumi Aoyagi, Hiroaki Honda, Yuichi Inadomi, Koji Inoue, Shigeru Ishizuki, Yasunori Kimura, Hidemi Komatsu, Motoyoshi Kurokawa, Kazuaki Murakami, Hidetomo Shibamura, Shuji Yamamura, Yunqing Yu: Performance prediction of large-scale parallell system and application using macro-level simulation. SC 2008: 20
30	EE	Naofumi Takagi, Kazuaki Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda: Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits. IEICE Transactions 91-C(3): 350-355 (2008)
29	EE	Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems. IEICE Transactions 91-C(4): 418-431 (2008)
28	EE	Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions. IEICE Transactions 91-C(4): 497-508 (2008)
27	EE	Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: An architecture framework for an adaptive extensible processor. The Journal of Supercomputing 45(3): 313-340 (2008)
2007
26	EE	Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: The effect of temperature on cache size tuning for low energy embedded systems. ACM Great Lakes Symposium on VLSI 2007: 453-456
25	EE	Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi: Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. DATE 2007: 325-330
24		Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. ESA 2007: 169-176
23	EE	Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260
22	EE	Toshiya Takami, Jun Maki, Jun-ichi Ooba, Yuichi Inadomi, Hiroaki Honda, Ryutaro Susukita, Koji Inoue, Taizo Kobayashi, Rie Nogita, Mutsumi Aoyagi: Multi-physics Extension of OpenFMO Framework CoRR abs/0707.2630: (2007)
21	EE	Mariko Sakamoto, Akira Katsuno, Go Sugizaki, Toshio Yoshida, Aiichiro Inoue, Koji Inoue, Kazuaki Murakami: A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips. IEICE Transactions 90-C(10): 1972-1982 (2007)
20	EE	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Transactions 90-D(12): 1956-1966 (2007)
2006
19	EE	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue: An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230
18	EE	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi: Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731
17	EE	Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4
16	EE	Koji Inoue: Return Address Protection on Cache Memories. IEICE Transactions 89-C(12): 1937-1947 (2006)
2005
15	EE	Shigeharu Matsusaka, Koji Inoue: A Cost Effective Spacial Redundancy with Data-Path Partitioning. ICITA (2) 2005: 51-56
14	EE	Hidekazu Tanaka, Koji Inoue: Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy. IEICE Transactions 88-A(12): 3274-3281 (2005)
13	EE	Reiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. IEICE Transactions 88-A(4): 862-868 (2005)
12	EE	Koji Inoue: Energy-security tradeoff in a secure cache architecture against buffer overflow attacks. SIGARCH Computer Architecture News 33(1): 81-89 (2005)
2003
11	EE	Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Reducing Access Count to Register-Files through Operand Reuse. Asia-Pacific Computer Systems Architecture Conference 2003: 112-121
2002
10	EE	Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Reducing power consumption of instruction ROMs by exploiting instruction frequency. APCCAS (2) 2002: 1-6
9	EE	Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue: Multiplier energy reduction through bypassing of partial products. APCCAS (2) 2002: 13-17
8	EE	Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A Low Energy Set-Associative I-Cache with Extended BTB. ICCD 2002: 187-
7	EE	Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa: Reducing energy consumption of video memory by bit-width compression. ISLPED 2002: 142-147
6	EE	Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A history-based I-cache for low-energy multimedia applications. ISLPED 2002: 148-153
5	EE	Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. PACS 2002: 18-32
4	EE	Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Register File Energy Reduction by Operand Data Reuse. PATMOS 2002: 278-288
2000
3	EE	Koji Inoue, Koji Kai, Kazuaki Murakami: Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. Intelligent Memory Systems 2000: 169-178
1999
2	EE	Koji Inoue, Koji Kai, Kazuaki Murakami: Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. HPCA 1999: 218-222
1	EE	Koji Inoue, Tohru Ishihara, Kazuaki Murakami: Way-predicting set-associative cache for high performance and low energy consumption. ISLPED 1999: 273-275

Coauthor Index

1	Hisashige Ando	[31]
2	Mutsumi Aoyagi	[22] [31]
3	Akira Fujimaki	[30]
4	Mizuka Fukagawa	[7]
5	Maziar Goudarzi	[24] [25] [26] [29] [32]
6	Hiroaki Honda	[22] [30] [31]
7	Yuichi Inadomi	[22] [31]
8	Aiichiro Inoue	[21]
9	Tohru Ishihara	[1]
10	Shigeru Ishizuki	[31]
11	Koji Kai	[2] [3]
12	Akira Katsuno	[21]
13	Yasunori Kimura	[31]
14	Taizo Kobayashi	[22]
15	Hidemi Komatsu	[31]
16	Reiko Komiya	[13]
17	Motoyoshi Kurokawa	[31]
18	Jun Maki	[22]
19	Shigeharu Matsusaka	[15]
20	Farhad Mehdipour	[17] [18] [19] [20] [23] [25] [27] [28] [33] [35]
21	Vasily G. Moshnyaga	[4] [5] [6] [7] [8] [9] [10] [11] [13]
22	Kazuaki Murakami	[1] [2] [3] [5] [6] [8] [10] [13] [17] [18] [19] [20] [21] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [35]
23	Rie Nogita	[22]
24	Hamid Noori	[17] [18] [19] [20] [23] [24] [25] [26] [27] [28] [29] [32] [33] [35]
25	Jun-ni Ohban	[9]
26	Jun-ichi Ooba	[22]
27	Mariko Sakamoto	[21]
28	Mehdi Sedighi	[18] [19]
29	Hidetomo Shibamura	[31]
30	Go Sugizaki	[21]
31	Ryutaro Susukita	[22] [31]
32	Hiroaki Takada	[34]
33	Naofumi Takagi	[30]
34	Toshiya Takami	[22]
35	Hiroshi Takamura	[4] [11]
36	Hidekazu Tanaka	[14]
37	Hiroyuki Tomiyama	[34]
38	Shuji Yamamura	[31]
39	Toshio Yoshida	[21]
40	Nobuyuki Yoshikawa	[30]
41	Yunqing Yu	[31]
42	Morteza Saheb Zamani	[17] [18] [19] [20] [23] [27] [35]
43	Gang Zeng	[34]
44	Junpei Zushi	[34]

Colors in the list of coauthors