| |
| 1990 | ||
|---|---|---|
| 2 | Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda: Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD 1990: 38-41 | |
| 1 | Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda: Multi-Level Logic Minimization Across Latch Boundaries. ICCAD 1990: 406-409 | |
| 1 | Masahiro Fujita | [1] [2] |
| 2 | Yusuke Matsunaga | [1] [2] |