| 2005 |
|---|
| 3 | EE | G. Peter Fang,
David C. Yeh,
David T. Zweidinger,
Lawrence A. Arledge Jr.,
Vinod Gupta:
Fast, accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicity.
ASP-DAC 2005: 1102-1106 |
| 1990 |
|---|
| 2 | | Kartikeya Mayaram,
Ping Yang,
Jue-Hsien Chern,
Richard Burch,
Lawrence A. Arledge Jr.,
Paul F. Cox:
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations.
ICCAD 1990: 446-449 |
| 1989 |
|---|
| 1 | EE | Jue-Hsien Chern,
John T. Maeda,
Lawrence A. Arledge Jr.,
Ping Yang:
SIERRA: a 3-D device simulator for reliability modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(5): 516-527 (1989) |
