Daniel Chillet

2008
13	EE	Daniel Chillet, Raphaël David, E. Grâce, Olivier Sentieys: Structure mémoire reconfigurable. Vers une structure de stockage faible consommation. Technique et Science Informatiques 27(1-2): 181-202 (2008)
2007
12	EE	Daniel Chillet, Sébastien Pillement, Olivier Sentieys: A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. IJCNN 2007: 102-107
2005
11		Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34
10		François Verdier, Jean-Christophe Prévotet, Amine Benkhelifa, Daniel Chillet, Sébastien Pillement: Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. ReCoSoC 2005: 71-78
2003
9	EE	Daniel Menard, Taofik Saïdi, Daniel Chillet, Olivier Sentieys: Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe. Technique et Science Informatiques 22(6): 783-803 (2003)
2002
8	EE	Daniel Menard, Daniel Chillet, François Charot, Olivier Sentieys: Automatic floating-point to fixed-point conversion for DSP code generation. CASES 2002: 270-276
7	EE	Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys: A Compilation Framework for a Dynamically Reconfigurable Architecture. FPL 2002: 1058-1067
6	EE	Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys: DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. IPDPS 2002
5	EE	Sébastien Pillement, Daniel Chillet, Olivier Sentieys: Behavioral IP Specification and Integration Framework for High-Level Design Reuse. ISQED 2002: 388-393
2001
4		Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys: A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC 2001: 51-62
2000
3	EE	Jean-Philippe Diguet, Daniel Chillet, Olivier Sentieys: A Framework for High Level Estimations of Signal Processing VLSI Implementations. VLSI Signal Processing 25(3): 261-284 (2000)
1999
2	EE	Daniel Chillet, Olivier Sentieys, Michel Corazza: Memory Unit Design for Real Time DSP Applications. Great Lakes Symposium on VLSI 1999: 260-
1	EE	J. O. Dedou, Daniel Chillet, Olivier Sentieys: Behavioral synthesis of asynchronous systems: a methodology. ISCAS (6) 1999: 370-373

Coauthor Index

1	Amine Benkhelifa	[10]
2	François Charot	[8]
3	Michel Corazza	[2]
4	Raphaël David	[4] [6] [7] [13]
5	J. O. Dedou	[1]
6	Jean-Philippe Diguet	[3]
7	Hritam Dutta	[11]
8	E. Grâce	[13]
9	Frank Hannig	[11]
10	Ronan Keryell	[11]
11	Alexey Kupriyanov	[11]
12	Daniel Menard	[8] [9] [11]
13	Renate Merker	[11]
14	Sébastien Pillement	[4] [5] [6] [7] [10] [12]
15	Bernard Pottier	[11]
16	Jean-Christophe Prévotet	[10]
17	Taofik Saïdi	[9]
18	Rainer Schaffer	[11]
19	Olivier Sentieys	[1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13]
20	Sebastian Siegel	[11]
21	Jürgen Teich	[11]
22	François Verdier	[10]