| |
| 2009 | ||
|---|---|---|
| 6 | Chia-Pin R. Liu: A Novel Floorplanning for Hierarchical VLSI Design. CATA 2009: 81-86 | |
| 2008 | ||
| 5 | Chia-Pin R. Liu: A Novel Synthesis for Dynamic CMOS Circuits. CAINE 2008: 112-117 | |
| 2007 | ||
| 4 | Chia-Pin R. Liu: Gate Model Extraction from CMOS Transistor Circuits. CAINE 2007: 193-198 | |
| 2006 | ||
| 3 | Chia-Pin R. Liu: Transistor-mapped binary decision diagram for CMOS circuits. CAINE 2006: 324-329 | |
| 2 | Chia-Pin R. Liu, Shaofeng Yang, Mahmound A. Manzoul: Traffic Monitoring for a Network Visualization Environment. Computers and Their Applications 2006: 84-89 | |
| 1999 | ||
| 1 | EE | Chia-Pin R. Liu, Jacob A. Abraham: Transistor Level Synthesis for Static CMOS Combinational Circuits. Great Lakes Symposium on VLSI 1999: 172-175 |
| 1 | Jacob A. Abraham | [1] |
| 2 | Mahmound A. Manzoul | [2] |
| 3 | Shaofeng Yang | [2] |