| 2007 |
|---|
| 9 | EE | Tetsuya Uemura,
T. Marukame,
K.-i. Matsuda,
Masafumi Yamamoto:
Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions.
ISMVL 2007: 49 |
| 2005 |
|---|
| 8 | EE | Shuichi Toyoda,
Noboru Niki,
Tetsuya Uemura,
Hiromu Nishitani:
Clinical support system using information aggregation and visualization for order data.
Systems and Computers in Japan 36(1): 12-24 (2005) |
| 2003 |
|---|
| 7 | EE | Tetsuya Uemura,
Masafumi Yamamoto:
Proposal of Four-Valued MRAM based on MTJ/RTD Structure.
ISMVL 2003: 273- |
| 2002 |
|---|
| 6 | EE | Tetsuya Uemura,
Pinaki Mazumder:
Rise time analysis of MOBILE circuit.
ISCAS (5) 2002: 864-867 |
| 2001 |
|---|
| 5 | | Tetsuya Uemura,
Toshio Baba:
A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors.
ISMVL 2001: 89-93 |
| 2000 |
|---|
| 4 | EE | Tetsuya Uemura,
Toshio Baba:
Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop.
ISMVL 2000: 305-310 |
| 1999 |
|---|
| 3 | EE | Tetsuya Uemura,
Pinaki Mazumder:
Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit.
Great Lakes Symposium on VLSI 1999: 158-161 |
| 1998 |
|---|
| 2 | EE | Toshio Baba,
Tetsuya Uemura:
Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits.
ISMVL 1998: 7-12 |
| 1997 |
|---|
| 1 | EE | Toshio Baba,
Tetsuya Uemura:
Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits .
ISMVL 1997: 41-46 |
