| 2009 |
|---|
| 11 | EE | M. Zid,
Abdelkrim Zitouni,
Adel Baganne,
Rached Tourki:
Nouvelles architectures génériques de NoC.
Technique et Science Informatiques 28(1): 101-133 (2009) |
| 2007 |
|---|
| 10 | EE | M. Zeghid,
Belgacem Bouallegue,
Adel Baganne,
M. Machhout,
Rached Tourki:
A Reconfigurable Implementation of the New Secure Hash Algorithm.
ARES 2007: 281-285 |
| 9 | EE | Philippe Coussy,
Emmanuel Casseau,
Pierre Bomel,
Adel Baganne,
Eric Martin:
Constrained algorithmic IP design for system-on-chip.
Integration 40(2): 94-105 (2007) |
| 2006 |
|---|
| 8 | EE | Philippe Coussy,
Emmanuel Casseau,
Pierre Bomel,
Adel Baganne,
Eric Martin:
A formal method for hardware IP design and integration under I/O and timing constraints.
ACM Trans. Embedded Comput. Syst. 5(1): 29-53 (2006) |
| 2004 |
|---|
| 7 | EE | Mehrez Marzougui,
Mohamed Abid,
Adel Baganne,
Rached Tourki:
Co-simulation and communication synthesis approach for intellectual properties based SoCs.
Computers & Electrical Engineering 30(5): 361-381 (2004) |
| 2003 |
|---|
| 6 | EE | Adel Baganne,
Imed Bennour,
Mehrez Elmarzougui,
Riadh Gaiech,
Eric Martin:
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration.
DATE 2003: 20250-20255 |
| 5 | | Philippe Coussy,
Adel Baganne,
Eric Martin:
Communication and Timing Constraints Analysis for IP Design and Integration.
VLSI-SOC 2003: 38-43 |
| 2002 |
|---|
| 4 | EE | Philippe Coussy,
Adel Baganne,
Eric Martin:
A design methodology for IP integration.
ISCAS (4) 2002: 711-714 |
| 1999 |
|---|
| 3 | EE | S. Gailhard,
Nathalie Julien,
Adel Baganne,
Eric Martin:
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures.
Great Lakes Symposium on VLSI 1999: 334-335 |
| 2 | EE | Adel Baganne,
Jean Luc Philippe,
Eric Martin:
A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller.
VLSI Signal Processing 22(1): 21-29 (1999) |
| 1997 |
|---|
| 1 | EE | Adel Baganne,
Jean Luc Philippe,
Eric Martin:
Hardware interface design for real time embedded systems.
Great Lakes Symposium on VLSI 1997: 58-63 |
