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2001 | ||
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8 | EE | Kanji Hirabayashi: An Algebraic Approach to Formal Verification of Microprocessors. J. Electronic Testing 17(6): 543-544 (2001) |
1998 | ||
7 | EE | Kanji Hirabayashi: A Method of Formal Verification of Cryptographic Circuits. J. Electronic Testing 13(3): 321-322 (1998) |
1996 | ||
6 | EE | Kanji Hirabayashi: Hazard simulation of sequential circuits. J. Electronic Testing 8(2): 215-217 (1996) |
1995 | ||
5 | EE | Kanji Hirabayashi: A parametric yield model. J. Electronic Testing 6(3): 331-332 (1995) |
1993 | ||
4 | EE | Kanji Hirabayashi: Delay fault simulation of sequential circuits. J. Electronic Testing 4(2): 131-135 (1993) |
1991 | ||
3 | EE | Kanji Hirabayashi: Self-checking CMOS circuits using pass-transistor logic. J. Electronic Testing 2(2): 205-208 (1991) |
1990 | ||
2 | EE | Masahisa Nakazawa, Susumu Nitta, Kanji Hirabayashi: Probabilistic fault grading based on activation checking and observability analysis. J. Electronic Testing 1(3): 235-238 (1990) |
1985 | ||
1 | Masahiko Kawamura, Kanji Hirabayashi: AFS : An Approximate Fault Simulator. ITC 1985: 717-721 |
1 | Masahiko Kawamura | [1] |
2 | Masahisa Nakazawa | [2] |
3 | Susumu Nitta | [2] |