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Kanji Hirabayashi

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2001
8EEKanji Hirabayashi: An Algebraic Approach to Formal Verification of Microprocessors. J. Electronic Testing 17(6): 543-544 (2001)
1998
7EEKanji Hirabayashi: A Method of Formal Verification of Cryptographic Circuits. J. Electronic Testing 13(3): 321-322 (1998)
1996
6EEKanji Hirabayashi: Hazard simulation of sequential circuits. J. Electronic Testing 8(2): 215-217 (1996)
1995
5EEKanji Hirabayashi: A parametric yield model. J. Electronic Testing 6(3): 331-332 (1995)
1993
4EEKanji Hirabayashi: Delay fault simulation of sequential circuits. J. Electronic Testing 4(2): 131-135 (1993)
1991
3EEKanji Hirabayashi: Self-checking CMOS circuits using pass-transistor logic. J. Electronic Testing 2(2): 205-208 (1991)
1990
2EEMasahisa Nakazawa, Susumu Nitta, Kanji Hirabayashi: Probabilistic fault grading based on activation checking and observability analysis. J. Electronic Testing 1(3): 235-238 (1990)
1985
1 Masahiko Kawamura, Kanji Hirabayashi: AFS : An Approximate Fault Simulator. ITC 1985: 717-721

Coauthor Index

1Masahiko Kawamura [1]
2Masahisa Nakazawa [2]
3Susumu Nitta [2]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)