Paul T. Hulina

1999
18	EE	David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor: Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. ICCD 1999: 146-151
17	EE	Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian: A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems. IEEE International Workshop on Rapid System Prototyping 1999: 222-
16	EE	David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor: Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use. IEEE International Workshop on Rapid System Prototyping 1999: 52-
15	EE	Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno: Computing in Memory Architectures for Digital Image Processing. MTDT 1999: 8-15
1995
14	EE	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor: A comparative evaluation of software techniques to hide memory latency. HICSS (1) 1995: 229
13		Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor: Program Balance and Its Impact on High Performance RISC Architectures. HPCA 1995: 370-379
1994
12		Ali Berrached, Paul T. Hulina, Lee D. Coraor: Structured Data Access Mechanisms for a Decoupled Computer Architecture. ICPP 1994: 285-289
11		Lizy Kurian John, Bermjae Choi, Paul T. Hulina, Lee D. Coraor: Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories. ICPP (1) 1994: 212-219
10		Lizy Kurian John, Paul T. Hulina, Lee D. Coraor: Memory Latency Effects in Decoupled Architectures. IEEE Trans. Computers 43(10): 1129-1139 (1994)
1992
9		Lizy Kurian John, Paul T. Hulina, Lee D. Coraor: Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module. ISCA 1992: 236-245
1991
8		Paul T. Hulina, Lee D. Coraor, Shih-Wei Sun: Performance Analysis of an Address Generation Coprocessor. ICPP (1) 1991: 136-143
7	EE	Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai: Classification and Performance Evaluation of Instruction Buffering Techniques. ISCA 1991: 150-159
1990
6		Paul T. Hulina, Lee D. Coraor: Coprocessor architectures for efficient address computation and memory accessing. Comput. Syst. Sci. Eng. 5(3): 137-146 (1990)
1987
5		Paul T. Hulina, Lee D. Coraor: A Hardware Memory Mapping Unit for Efficient Address Computation. ICPP 1987: 340-343
4		Lee D. Coraor, Paul T. Hulina, Orlando A. Morean: A General Model for Memory-Based Finite-State Machines. IEEE Trans. Computers 36(2): 175-184 (1987)
1985
3		Lee D. Coraor, Paul T. Hulina: A Reconfigurable Multiprocessor. ICPP 1985: 649-651
1972
2		Jon G. Bredeson, Paul T. Hulina: Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits Information and Control 20(2): 114-124 (1972)
1970
1		Jon G. Bredeson, Paul T. Hulina: Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits FOCS 1970: 104-108

Coauthor Index

1	Sanjay Balasubramanian	[17]
2	Ali Berrached	[12]
3	Jon G. Bredeson	[1] [2]
4	Bermjae Choi	[11]
5	Lee D. Coraor	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [18]
6	Scott Deno	[15] [17] [18]
7	Praveen Guddeti	[16]
8	Lizy Kurian John (Lizy K. John)	[7] [9] [10] [11] [13] [14]
9	David L. Landis	[15] [16] [17] [18]
10	Dhamir N. Mannai	[7]
11	Orlando A. Morean	[4]
12	Vinod Reddy	[13] [14]
13	Luke Roth	[15] [18]
14	Shih-Wei Sun	[8]

Colors in the list of coauthors