| 2009 |
| 33 | EE | Joseph Devietti,
Brandon Lucia,
Luis Ceze,
Mark Oskin:
DMP: deterministic shared memory multiprocessing.
ASPLOS 2009: 85-96 |
| 2008 |
| 32 | EE | Martha Mercaldi Kim,
John D. Davis,
Mark Oskin,
Todd M. Austin:
Polymorphic On-Chip Networks.
ISCA 2008: 101-112 |
| 31 | EE | Lucas Kreger-Stickles,
Mark Oskin:
Microcoded Architectures for Ion-Tap Quantum Computers.
ISCA 2008: 165-176 |
| 30 | EE | Michael Ross,
Mark Oskin:
Quantum computing.
Commun. ACM 51(7): 12-13 (2008) |
| 29 | EE | Mark Oskin:
The revolution inside the box.
Commun. ACM 51(7): 70-78 (2008) |
| 2007 |
| 28 | EE | Martha Mercaldi Kim,
Mojtaba Mehrara,
Mark Oskin,
Todd M. Austin:
Architectural implications of brick and mortar silicon manufacturing.
ISCA 2007: 244-253 |
| 27 | EE | Steven Swanson,
Andrew Schwerin,
Martha Mercaldi,
Andrew Petersen,
Andrew Putnam,
Ken Michelson,
Mark Oskin,
Susan J. Eggers:
The WaveScalar architecture.
ACM Trans. Comput. Syst. 25(2): (2007) |
| 26 | EE | John Wawrzynek,
David A. Patterson,
Mark Oskin,
Shih-Lien Lu,
Christoforos E. Kozyrakis,
James C. Hoe,
Derek Chiou,
Krste Asanovic:
RAMP: Research Accelerator for Multiple Processors.
IEEE Micro 27(2): 46-57 (2007) |
| 2006 |
| 25 | EE | Martha Mercaldi,
Steven Swanson,
Andrew Petersen,
Andrew Putnam,
Andrew Schwerin,
Mark Oskin,
Susan J. Eggers:
Instruction scheduling for a tiled dataflow architecture.
ASPLOS 2006: 141-150 |
| 24 | EE | Steven Swanson,
Andrew Putnam,
Martha Mercaldi,
Martha Mercaldi,
Ken Michelson,
Andrew Petersen,
Andrew Schwerin,
Mark Oskin,
Susan J. Eggers:
Area-Performance Trade-offs in Tiled Dataflow Architectures.
ISCA 2006: 314-326 |
| 23 | EE | Andrew Petersen,
Andrew Putnam,
Martha Mercaldi,
Andrew Schwerin,
Susan J. Eggers,
Steven Swanson,
Mark Oskin:
Reducing control overhead in dataflow architectures.
PACT 2006: 182-191 |
| 22 | EE | Martha Mercaldi,
Steven Swanson,
Andrew Petersen,
Andrew Putnam,
Andrew Schwerin,
Mark Oskin,
Susan J. Eggers:
Modeling instruction placement on a spatial architecture.
SPAA 2006: 158-169 |
| 21 | EE | Rodney Van Meter,
Mark Oskin:
Architectural implications of quantum computing technologies.
JETC 2(1): 31-63 (2006) |
| 2005 |
| 20 | EE | Steven Balensiefer,
Lucas Kreger-Stickles,
Mark Oskin:
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures.
ISCA 2005: 186-196 |
| 2004 |
| 19 | EE | Timothy Sherwood,
Mark Oskin,
Brad Calder:
Balancing design options with Sherpa.
CASES 2004: 57-68 |
| 18 | | Dean Copsey,
Mark Oskin,
Frederic T. Chong:
Ions, atoms, and bits: An architectural approach to quantum computing.
Advances in Computers 61: 276-318 (2004) |
| 17 | EE | Nemanja Isailovic,
Mark Whitney,
Yatish Patel,
John Kubiatowicz,
Dean Copsey,
Frederic T. Chong,
Isaac L. Chuang,
Mark Oskin:
Datapath and control for quantum wires.
TACO 1(1): 34-61 (2004) |
| 2003 |
| 16 | EE | Mark Oskin,
Frederic T. Chong,
Isaac L. Chuang,
John Kubiatowicz:
Building Quantum Wires: The Long and the Short of It.
ISCA 2003: 374-385 |
| 15 | EE | Steven Swanson,
Ken Michelson,
Andrew Schwerin,
Mark Oskin:
WaveScalar.
MICRO 2003: 291-302 |
| 14 | EE | Dean Copsey,
Mark Oskin,
Tzvetan S. Metodi,
Frederic T. Chong,
Isaac L. Chuang,
John Kubiatowicz:
The effect of communication costs in solid-state quantum computing architectures.
SPAA 2003: 65-74 |
| 13 | EE | Diana Keen,
Mark Oskin,
Justin Hensley,
Frederic T. Chong:
Cache Coherence in Intelligent Memory Systems.
IEEE Trans. Computers 52(7): 960-966 (2003) |
| 2002 |
| 12 | EE | Ravishankar Rao,
Mark Oskin,
Frederic T. Chong:
HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space.
HiPC 2002: 620-629 |
| 11 | EE | Chris J. Thompson,
Sahngyun Hahn,
Mark Oskin:
Using modern graphics architectures for general-purpose computing: a framework and analysis.
MICRO 2002: 306-317 |
| 10 | EE | Mark Oskin,
Frederic T. Chong,
Isaac L. Chuang:
A Practical Architecture for Reliable Quantum Computers.
IEEE Computer 35(1): 79-87 (2002) |
| 9 | EE | Mark Oskin,
Frederic T. Chong,
Matthew K. Farrens:
Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation.
J. Instruction-Level Parallelism 4: (2002) |
| 8 | EE | Mark Oskin,
Diana Keen,
Justin Hensley,
Lucian Vlad Lita,
Frederic T. Chong:
Operating Systems Techniques for Parallel Computation in Intelligent Memory.
Parallel Processing Letters 12(3-4): 311-326 (2002) |
| 2001 |
| 7 | | Frederic T. Chong,
Christoforos E. Kozyrakis,
Mark Oskin:
Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers
Springer 2001 |
| 2000 |
| 6 | EE | Mark Oskin,
Diana Keen,
Justin Hensley,
Lucian Vlad Lita,
Frederic T. Chong:
Reducing Cost and Tolerating Defects in Page-based Intelligent Memory.
ICCD 2000: 276- |
| 5 | EE | Mark Oskin,
Frederic T. Chong,
Matthew K. Farrens:
HLS: combining statistical and symbolic simulation to guide microprocessor designs.
ISCA 2000: 71-82 |
| 4 | | Mark Oskin,
Lucian Vlad Lita,
Frederic T. Chong,
Justin Hensley,
Diana Keen:
Algorithmic Complexity with Page-Based Intelligent Memory.
Parallel Processing Letters 10(1): 99-110 (2000) |
| 1999 |
| 3 | EE | Mark Oskin,
Frederic T. Chong,
Timothy Sherwood:
ActiveOS: Virtualizing Intelligent Memory.
ICCD 1999: 202- |
| 2 | EE | Mark Oskin,
Justin Hensley,
Diana Keen,
Frederic T. Chong,
Matthew K. Farrens,
Aneet Chopra:
Exploiting ILP in Page-based Intelligent Memory.
MICRO 1999: 208-218 |
| 1998 |
| 1 | EE | Mark Oskin,
Frederic T. Chong,
Timothy Sherwood:
Active Pages: A Computation Model for Intelligent Memory.
ISCA 1998: 192-203 |