| 2007 |
|---|
| 32 | EE | Haruhiko Kaneko,
Eiji Fujiwara:
Joint Source-Cryptographic-Channel Coding Based on Linear Block Codes.
AAECC 2007: 158-167 |
| 31 | EE | Haruhiko Kaneko,
Eiji Fujiwara:
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks.
DFT 2007: 349-358 |
| 30 | EE | Kazuyoshi Suzuki,
Toshihiko Kashiyama,
Eiji Fujiwara:
A General Class of M-Spotty Byte Error Control Codes.
IEICE Transactions 90-A(7): 1418-1427 (2007) |
| 29 | EE | Kazuteru Namba,
Eiji Fujiwara:
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings.
Systems and Computers in Japan 38(8): 54-60 (2007) |
| 2006 |
|---|
| 28 | EE | Hiroyuki Ohde,
Haruhiko Kaneko,
Eiji Fujiwara:
Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems.
DFT 2006: 175-183 |
| 27 | EE | Kazuyoshi Suzuki,
Toshihiko Kashiyama,
Eiji Fujiwara:
Complex M-Spotty Byte Error Control Codes.
IEICE Transactions 89-A(9): 2396-2404 (2006) |
| 2005 |
|---|
| 26 | EE | Jien-Chung Lo,
Yu-Lun Wan,
Eiji Fujiwara:
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes.
DFT 2005: 120-130 |
| 25 | EE | Ganesan Umanesan,
Eiji Fujiwara:
Parallel Decoding Cyclic Burst Error Correcting Codes.
IEEE Trans. Computers 54(1): 87-92 (2005) |
| 2004 |
|---|
| 24 | EE | Haruhiko Kaneko,
Mariko Numakami,
Eiji Fujiwara:
Nonsystematic M-Ary Asymmetric Error Correcting Codes Designed by Multilevel Coding Method.
PRDC 2004: 219-226 |
| 23 | EE | Haruhiko Kaneko,
Eiji Fujiwara:
A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices.
IEEE Trans. Computers 53(2): 159-167 (2004) |
| 2003 |
|---|
| 22 | EE | Haruhiko Kaneko,
Eiji Fujiwara:
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols.
DFT 2003: 242-249 |
| 21 | EE | Ganesan Umanesan,
Eiji Fujiwara:
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes.
IEEE Trans. Computers 52(7): 835-847 (2003) |
| 2002 |
|---|
| 20 | EE | Ganesan Umanesan,
Eiji Fujiwara:
A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems.
PRDC 2002: 247-256 |
| 2001 |
|---|
| 19 | EE | Kazuteru Namba,
Eiji Fujiwara:
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities.
DFT 2001: 299-307 |
| 18 | EE | Kazuteru Namba,
Eiji Fujiwara:
A class of systematic m-ary single-symbol error correcting codes.
Systems and Computers in Japan 32(6): 21-28 (2001) |
| 2000 |
|---|
| 17 | EE | Masato Kitakami,
Hongyuan Chen,
Eiji Fujiwara:
Evaluations of Burst Error Recovery for VF Arithmetic Coding.
DFT 2000: 183-191 |
| 16 | EE | Ganesan Umanesan,
Eiji Fujiwara:
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems.
DFT 2000: 192-200 |
| 1999 |
|---|
| 15 | EE | Kiattichai Saowapa,
Haruhiko Kaneko,
Eiji Fujiwara:
Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability.
DFT 1999: 284-292 |
| 1998 |
|---|
| 14 | | Eiji Fujiwara,
Tepparit Ritthongpitak,
Masato Kitakami:
Optimal Two-Level Unequal Error Control Codes for Computer Systems.
IEEE Trans. Computers 47(12): 1313-1325 (1998) |
| 1997 |
|---|
| 13 | | Mitsuru Hamada,
Eiji Fujiwara:
A Class of Error Control Codes for Byte Organized Memory Systems —SbEC-(Sb+S)ED Codes—.
IEEE Trans. Computers 46(1): 105-109 (1997) |
| 1996 |
|---|
| 12 | | Tepparit Ritthongpitak,
Masato Kitakami,
Eiji Fujiwara:
Optimal Two-Level Unequal Error Control Codes for Computer Systems.
FTCS 1996: 190-199 |
| 11 | | Jien-Chung Lo,
Eiji Fujiwara:
Probability to Achieve TSC Goal.
IEEE Trans. Computers 45(4): 450-460 (1996) |
| 1995 |
|---|
| 10 | | Eiji Fujiwara,
Masato Kitakami:
A Class of Optimal Fixed-Byte Error Protection Codes for Computer Systems.
FTCS 1995: 310-319 |
| 1994 |
|---|
| 9 | | Eiji Fujiwara,
Masato Kitakami:
A class of error-correcting codes for byte-organized memory systems.
IEEE Transactions on Information Theory 40(6): 1857-1865 (1994) |
| 1993 |
|---|
| 8 | | Eiji Fujiwara,
Masaharu Tanaka:
A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation.
DFT 1993: 183-190 |
| 7 | | Jien-Chung Lo,
Eiji Fujiwara:
A Probabilistic Measurement for Totally Self-Checking Circuits.
DFT 1993: 263-270 |
| 6 | | Eiji Fujiwara,
Masato Kitakami:
A Class of Error Locating Codes for Byte-Organized Memory Systems.
FTCS 1993: 110-119 |
| 1992 |
|---|
| 5 | | Eiji Fujiwara,
Mitsuru Hamada:
Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems.
FTCS 1992: 494-501 |
| 1990 |
|---|
| 4 | | Eiji Fujiwara,
Dhiraj K. Pradhan:
Error-Control Coding in Computers.
IEEE Computer 23(7): 63-72 (1990) |
| 1987 |
|---|
| 3 | | Eiji Fujiwara,
Kohji Matsuoka:
A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing.
IEEE Trans. Computers 36(1): 86-93 (1987) |
| 1984 |
|---|
| 2 | | Eiji Fujiwara,
Nobuo Mutoh,
Kohji Matsuoka:
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing.
IEEE Trans. Computers 33(6): 578-583 (1984) |
| 1982 |
|---|
| 1 | | Shigeo Kaneda,
Eiji Fujiwara:
Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems.
IEEE Trans. Computers 31(7): 596-602 (1982) |
