DFT 2001:
San Francisco,
CA,
USA
16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings.
IEEE Computer Society 2001, ISBN 0-7695-1203-8 BibTeX
@proceedings{DBLP:conf/dft/2001,
title = {16th IEEE International Symposium on Defect and Fault-Tolerance
in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco,
CA, USA, Proceedings},
booktitle = {DFT},
publisher = {IEEE Computer Society},
year = {2001},
isbn = {0-7695-1203-8},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Wafer Scale
Yield
Dependable Design
Testing Techniques 1
Fault-Tolerance in Arrays
Fault Detection
FPGA Based Applications
- Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi:
A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application.
191-199
Electronic Edition (IEEE Computer Society DL) BibTeX
- Kaijie Wu, Ramesh Karri:
Idle Cycles Based Concurrent Error Detection of RC6 Encryption.
200-205
Electronic Edition (IEEE Computer Society DL) BibTeX
- Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey:
Fast Run-Time Fault Location in Dependable FPGA-Based Applications.
206-214
Electronic Edition (IEEE Computer Society DL) BibTeX
- Jayabrata Ghosh-Dastidar, Nur A. Touba:
Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability.
215-220
Electronic Edition (IEEE Computer Society DL) BibTeX
- Xiaoling Sun, Jian Xu, Pieter M. Trouborst:
Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules.
221-
Electronic Edition (IEEE Computer Society DL) BibTeX
Fault Injection
Testing Techniques 2
Error Correcting Codes
Mixed Signal Circuits
Defect Analysis
- Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak:
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.
357-365
Electronic Edition (IEEE Computer Society DL) BibTeX
- Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams:
Defect Analysis and a New Fault Model for Multi-port SRAMs.
366-374
Electronic Edition (IEEE Computer Society DL) BibTeX
- Mykola Blyzniuk, Irena Kazymyra:
Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell Library.
375-383
Electronic Edition (IEEE Computer Society DL) BibTeX
- Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz:
CMOS Standard Cells Characterization for Defect Based Testing.
384-
Electronic Edition (IEEE Computer Society DL) BibTeX
Self-Checking and Fail-Safe Circuits
Fault-Tolerant Techniques
- Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim:
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture.
427-435
Electronic Edition (IEEE Computer Society DL) BibTeX
- Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui:
On Variable-Shift-Based Fault Compensation of Fuzzy Controllers.
436-444
Electronic Edition (IEEE Computer Society DL) BibTeX
- John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici:
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs.
445-454
Electronic Edition (IEEE Computer Society DL) BibTeX
- Salvatore Pontarelli, Gian-Carlo Cardarilli, A. Malvoni, Marco Ottavi, Marco Re, Adelio Salsano:
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology.
455-460
Electronic Edition (IEEE Computer Society DL) BibTeX
- Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey:
Performance Evaluation of Checksum-Based ABFT.
461-
Electronic Edition (IEEE Computer Society DL) BibTeX
Copyright © Sat May 16 23:06:35 2009
by Michael Ley (ley@uni-trier.de)
