DFT 1993: Venice, Italy

@proceedings{DBLP:conf/dft/1993,
  editor    = {Fabrizio Lombardi and
               Mariagiovanna Sami and
               Yvon Savaria and
               Renato Stefanelli},
  title     = {The IEEE International Workshop on Defect and Fault Tolerance
               in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings},
  booktitle = {DFT},
  publisher = {IEEE Computer Society},
  year      = {1993},
  isbn      = {0-8186-3502-9},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Fault Tolerant Architectures

• A. Dell'Acqua, M. Hansen, S. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, A. Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, S. Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson: System Level Policies for Fault Tolerance Issues in the FERMI Project. 1-8 BibTeX
• R. Rochet, Régis Leveugle, Gabriele Saucier: Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. 9-16 BibTeX

Fault Tolerant Structures

• Liangkung Lin, G. Robert Redinbo: Block Implementation of Fault-Tolerant LMS Adaptive FIR Filters. 17-24 BibTeX
• Hee Yong Youn, Kyung Ook Lee: Fault-Tolerant Sorting Using VLSI Processor Arrays. 25-32 BibTeX
• Gian-Carlo Cardarilli, M. Di Zenzo, Pat O. Pistilli, Adelio Salsano: A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks. 33-40 BibTeX
• Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey: High Level Synthesis Techniques for Efficient Built-In-Self Repair. 41-48 BibTeX
• Hannu Kari, Heikki Saikkonen, Fabrizio Lombardi: Detection of Defective Media in Disks. 49-55 BibTeX

Reconfiguration

• Hussain Al-Asaad, Elias S. Manolakos: A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures. 56-63 BibTeX
• Chor Ping Low, Hon Wai Leong: On the Reconfiguration of Degradable VLSI/WSI Arrays. 64-71 BibTeX
• Chouki Aktouf, Chantal Robach, Guy Mazaré, J. Johansson: Functional Testing and Reconfiguration of MIMD Machines. 72-79 BibTeX
• Hideo Ito: A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. 80-87 BibTeX
• José Salinas, Fabrizio Lombardi: On the Reconfigurable Operation of Arrays with Defects for Image Processing. 88-95 BibTeX

Physical Analysis

• A. Kerek: Front-end Electronics in the Radiation Environment of LHC. 96-100 BibTeX
• Víctor H. Champac, Antonio Rubio, Joan Figueras: Analysis of the Floating Gate Defect in CMOS. 101-108 BibTeX
• Antonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. 109-116 BibTeX
• Hua Xue, Chennian Di, Jochen A. G. Jess: Fast Multi-Layer Critical Area Computation. 117-124 BibTeX

Yield Modeling

• Enrico Ferrati, Magneti Marelli: TEh Reliability of the Integrated Circuits in Automotive Industry. 125-126 BibTeX
• Randall S. Collica: A Logistic Regression Yield Model for SRAM Bit Fail Patterns. 127-135 BibTeX
• Charles H. Stapper, J. A. Patrick, R. J. Rosner: Yield Model for ASIC and Processor Chips. 136-143 BibTeX
• J. Crépeau, Claude Thibeault, Yvon Savaria: Some Results on Yield and Local Design Rule Relaxation. 144-151 BibTeX
• Frederic Duvivier, M. Rivier, B. Burtschy, J. J. Charlot: Use of a Segmentation Technique to Analyze the Variability of the Yield of a Mature CMOS SRAM. 152-158 BibTeX

Design for Yield

• Zahava Koren, Israel Koren: Does the Floorplan of a Chip Affect Its Yield? 159-166 BibTeX
• Israel A. Wagner, Israel Koren: An Interactive Yield Estimator as a VLSI CAD Tool. 167-174 BibTeX
• Venkat K. R. Chiluvuri, Israel Koren: Topological Optimization of PLAs for Yield Enhancement. 175-182 BibTeX
• Eiji Fujiwara, Masaharu Tanaka: A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. 183-190 BibTeX

Testing Techniques

• Giacomo Buonanno, Franco Fummi, Donatella Sciuto: Fault Detection in Sequential Circuits through Functional Testing. 191-198 BibTeX
• M. Rullán, F. C. Blom, J. Oliver, C. Ferrer: Layout Level Design for Testability Strategy Applied to a CMOS Cell Library. 199-206 BibTeX
• Michel Renovell, Joan Figueras: Current Testing Viability in Dynamic CMOS Circuits. 207-214 BibTeX
• David Wessels, Jon C. Muzio: Probabilistic Identification of Critical Components for Circuit Delays. 215-222 BibTeX
• Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza: Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. 223-230 BibTeX

Testable Architectures

• Graham Frearson: The T9000 Transputer: A Practical Example of the Application of Standard Test Techniques. 231-238 BibTeX
• Egor S. Sogomonyan, Michael Gössel: Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection. 239-246 BibTeX
• Xiaoling Sun, Micaela Serra: Design and Implementation of a Merged On-Line and Off-Line Self Textable Architecture. 247-254 BibTeX
• Dah-Yea Wei, Jung Hwan Kim, T. R. N. Rao: Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays. 255-262 BibTeX

Self-Checking and Error-Correcting Architectures

• Jien-Chung Lo, Eiji Fujiwara: A Probabilistic Measurement for Totally Self-Checking Circuits. 263-270 BibTeX
• Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò: Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. 271-278 BibTeX
• Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò: A Highly Testable 1-out-of-3 CMOS Checker. 279-286 BibTeX
• Yuang-Ming Hsu, Earl E. Swartzlander Jr.: VLSI Concurrent Error Correcting Adders and Multipliers. 287-294 BibTeX

Defect/Fault Tolerance in Analog Systems

• D. Taylor, P. S. A. Evans, D. Marland: Functional Testing of Linear Circuits Using Transient Response Analysis. 295-302 BibTeX
• Alessandra Fanni, Alessandro Giua, Enrico Sandoli: Neural Networks for Multiple Fault Diagnosis in Analog Circuits. 303-310 BibTeX
• P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Realistic Fault Analysis of CMOS Analog Building Blocks. 311-318 BibTeX
• Manoj Sachdev: Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier. 319-326 BibTeX
• Nagendra Kumar, Philippe O. Pouliquen, Andreas G. Andreou: Device Mismatch Limitations on the Performance of a Hamming Distance Classifier. 327-334 BibTeX