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Frédéric Bancel

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2007
9EEOlivier Faurax, Assia Tria, Laurent Freund, Frédéric Bancel: Robustness of circuits under delay-induced faults : test of AES with the PAFI tool. IOLTS 2007: 185-186
8EEDavid Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Securing Scan Control in Crypto Chips. J. Electronic Testing 23(5): 457-464 (2007)
2006
7EEDavid Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: A secure scan design methodology. DATE 2006: 1177-1178
6EEDavid Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Secure Scan Techniques: A Comparison. IOLTS 2006: 119-124
5EENicolas Valette, Lionel Torres, Gilles Sassatelli, Frédéric Bancel: Securing embedded programmable gate arrays in secure circuits. IPDPS 2006
2005
4 Nicolas Valette, Lionel Torres, Frédéric Bancel, Nicolas Bérard: Integration of Reconfigurable Logic on Secure Circuits. ReCoSoC 2005: 163-168
2004
3EEDavid Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell: Scan Design and Secure Chip. IOLTS 2004: 219-226
1993
2 Yves Bertrand, Frédéric Bancel, Michel Renovell: Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. ITC 1993: 989-997
1 Yves Bertrand, Frédéric Bancel, Michel Renovell: A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. VLSI Design 1993: 51-54

Coauthor Index

1Nicolas Bérard [3] [4]
2Yves Bertrand [1] [2]
3Olivier Faurax [9]
4Marie-Lise Flottes [3] [6] [7] [8]
5Laurent Freund [9]
6David Hély [3] [6] [7] [8]
7Michel Renovell [1] [2] [3]
8Bruno Rouzeyre [3] [6] [7] [8]
9Gilles Sassatelli [5]
10Lionel Torres [4] [5]
11Assia Tria [9]
12Nicolas Valette [4] [5]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)