2007 |
9 | EE | Olivier Faurax,
Assia Tria,
Laurent Freund,
Frédéric Bancel:
Robustness of circuits under delay-induced faults : test of AES with the PAFI tool.
IOLTS 2007: 185-186 |
8 | EE | David Hély,
Frédéric Bancel,
Marie-Lise Flottes,
Bruno Rouzeyre:
Securing Scan Control in Crypto Chips.
J. Electronic Testing 23(5): 457-464 (2007) |
2006 |
7 | EE | David Hély,
Frédéric Bancel,
Marie-Lise Flottes,
Bruno Rouzeyre:
A secure scan design methodology.
DATE 2006: 1177-1178 |
6 | EE | David Hély,
Frédéric Bancel,
Marie-Lise Flottes,
Bruno Rouzeyre:
Secure Scan Techniques: A Comparison.
IOLTS 2006: 119-124 |
5 | EE | Nicolas Valette,
Lionel Torres,
Gilles Sassatelli,
Frédéric Bancel:
Securing embedded programmable gate arrays in secure circuits.
IPDPS 2006 |
2005 |
4 | | Nicolas Valette,
Lionel Torres,
Frédéric Bancel,
Nicolas Bérard:
Integration of Reconfigurable Logic on Secure Circuits.
ReCoSoC 2005: 163-168 |
2004 |
3 | EE | David Hély,
Marie-Lise Flottes,
Frédéric Bancel,
Bruno Rouzeyre,
Nicolas Bérard,
Michel Renovell:
Scan Design and Secure Chip.
IOLTS 2004: 219-226 |
1993 |
2 | | Yves Bertrand,
Frédéric Bancel,
Michel Renovell:
Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits.
ITC 1993: 989-997 |
1 | | Yves Bertrand,
Frédéric Bancel,
Michel Renovell:
A DFT Technique to Improve ATPG Efficiency for Sequential Circuits.
VLSI Design 1993: 51-54 |