DFT 1997: Paris, France

1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France. IEEE Computer Society 1997, ISBN 0-8186-8168-3 BibTeX

@proceedings{DBLP:conf/dft/1997,
  title     = {1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT
               '97), 20-22 October 1997, Paris, France},
  booktitle = {DFT},
  publisher = {IEEE Computer Society},
  year      = {1997},
  isbn      = {0-8186-8168-3},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Critical Area

Witold A. Pleskacz, Wojciech Maly:
Improved Yield Model for Submicron Domain. 2-10
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Sandra Levasseur, Frederic Duvivier:
Application of a yield model merging critical areas and defectivity to industrial products. 11-19
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Gerard A. Allan, Anthony J. Walton:
Efficient critical area estimation for arbitrary defect shapes. 20-28
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Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. 29-37
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Zhan Chen, Israel Koren:
Crosstalk Minimization in Three-Layer HVH Channel Routing. 38-43
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Yield Management

Pascal Bichebois, Pierre Mathery:
Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits. 44-52
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Anil Gandhi, Stacy Hall, Ron Harris:
An examination of empirically derived within-die local probabilities of failure. 53-61
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Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken:
Detection of Yield Trends. 62-68
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Allan Y. Wong:
A Statistical Approach To Identify Semiconductor Process Equipment Related Yield Problems. 69-75
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Test and Test Generation

D. G. Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi:
Testing of programmable logic devices (PLD) with faulty resources. 76-84
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Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami:
Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. 85-93
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Chouki Aktouf, Ghassan Al Hayek, Chantal Robach:
Concurrent testing of VLSI digital signal processors using mutation based testing. 94-99
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Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski:
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations. 100-109
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Self Checking and Codin

Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra:
Fast and area-time efficient Berger code checkers. 110-118
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Stanislaw J. Piestrak:
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. 119-127
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Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos:
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. 128-136
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Cecilia Metra, Michele Favalli, Bruno Riccò:
Compact and low power on-line self-testing voting scheme. 137-147
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Cost Modeling

Michel Kafrouni, Claude Thibeault, Yvon Savaria:
A Cost Model for VLSI / MCM Systems. 148-156
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Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault:
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. 157-165
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Israel Koren, Zahava Koren:
Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs. 166-174
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John R. Samson Jr., Wilfrido A. Moreno, Fernando J. Falquez:
Validating fault tolerant designs using laser fault injection (LFI). 175-185
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Fault Tolerance

Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi:
Multiple fault detection in logic resources of FPGAs. 186-194
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X. Wendling, H. Chauvet, Lionel Revéret, R. Rochet, Régis Leveugle:
Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. 195-203
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Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli:
Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. 204-211
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Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar:
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. 212-217
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Fault Tolerance II

Itsuo Takanami, Tadayoshi Horita:
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. 218-226
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Nobuo Tsuda:
Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node Coloring. 227-233
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Error Recovery

Michele Favalli, Cecilia Metra:
Low-level error recovery mechanism for self-checking sequential circuits. 234-242
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W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. 243-251
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Xiaoling Sun, Wes Tutak:
Error Identification and Data Recovery in MISR-based Data Compaction. 252-260
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F. Distante, Mariagiovanna Sami, Renato Stefanelli:
Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. 261-271
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Error Detection

Alvernon Walker, Algernon P. Henry, Parag K. Lala:
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. 272-280
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Christopher G. Knight, Adit D. Singh, Victor P. Nelson:
An IDDQ Sensor for Concurrent Timing Error Detection. 281-289
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Cristiana Bolchini, Donatella Sciuto, Fabio Salice:
Designing Networks with Error Detection Properties through the Fault-Error Relation. 290-297
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Anna Antola, Vincenzo Piuri, Mariagiovanna Sami:
Semi-Concurrent Error Detection in Data Paths. 298-306
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Michael Gössel, Sebastian T. J. Fenn, David Taylor:
On-line error detection for finite field multipliers. 307-312
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