CHDL 1993: Ottawa, Ontario, Canada

@proceedings{DBLP:conf/chdl/1993,
  editor    = {David Agnew and
               Luc J. M. Claesen and
               Raul Camposano},
  title     = {Computer Hardware Description Languages and their Applications,
               Proceedings of the 11th IFIP WG10.2 International Conference
               on Computer Hardware Description Languages and their Applications
               - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with
               IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993},
  booktitle = {CHDL},
  publisher = {North-Holland},
  series    = {IFIP Transactions},
  volume    = {A-32},
  year      = {1993},
  isbn      = {0-444-81641-0},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Mario Barbacci: Real Time Distributed Systems. 3-12 BibTeX

Session: BDD-based Design and Analysis Techniques

• Edmund M. Clarke, Orna Grumberg, Hiromi Hiraishi, Somesh Jha, David E. Long, Kenneth L. McMillan, Linda A. Ness: Verification of the Futurebus+ Cache Coherence Protocol. 15-30 BibTeX
• Paolo Camurati, Fulvio Corno, Paolo Prinetto: Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation. 31-44 BibTeX
• Klaus Schneider, Ramayya Kumar, Thomas Kropf: Hardware-Verification using First Order BDDs. 45-62 BibTeX

Session: HDL-based Design Methods

• Klaus Buchenrieder, Alexander Sedlmeier, Christian Veith: HW/SW Co-Design with PRAMs Using CoDES. 65-78 BibTeX
• Flávio Rech Wagner: Prevail-DM: A Framework-Based Environment for Formal Hardware Verification. 79-96 BibTeX
• C. Norris Ip, David L. Dill: Better Verification Through Symmetry. 97-111 BibTeX

Session: Synthesis and Verification

• Michel Allemand: A Rewriting Based Method for the Formal Verification of Microprocessors. 115-122 BibTeX
• J. W. Gambles, Phillip J. Windley: Reasoning about the VHDL Standard Logic Package Signal Data Type. 123-130 BibTeX
• Xing-Jian Xu, Mitsuru Ishizuka: An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area. 131-138 BibTeX
• Bhaskar Bose, Steven D. Johnson, Shyamsundar Pullela: Integrating Boolean Verification with Formal Derivation. 139-146 BibTeX
• Francisco Corella: Automated High-level Verification Against Clocked Algorithmic Specifications. 147-154 BibTeX
• Stefan Krischer: The Backward Walk Approach in FSM Verification. 155-162 BibTeX
• Edmund M. Clarke: Automatic Verification of Sequential Circuit Designs. 165 BibTeX

Session: Protocol Specification

• Kamlesh Rath, Steven D. Johnson: Toward a Basis for Protocol Specification and Process Decomposition. 169-186 BibTeX
• Wolfgang Glunz, Thomas Kruse, Torsten Rössel, Dieter Monjau: Integrating SDL and VHDL for System-Level Hardware Design. 187-204 BibTeX

Session: Formal Reasoning about Regular Structures

• Alan Dent, Keith Hanna: Reasoning about Array Structure Using a Dependently Typed Logic. 207-224 BibTeX
• Laurence Pierre: VHDL Description and Formal Verification of Systolic Multipliers. 225-242 BibTeX
• Robin Sharp, Ole Rasmussen: Transformational Rewriting with Ruby. 243-260 BibTeX

Session: High Level Synthesis

• Roger P. Ang, Nikil D. Dutt: A Representation for the Binding of RT-Component Functionality to HDL Behavior. 263-280 BibTeX
• Ram Mandayam, Ranga Vemuri: Performance Specification and Measurement. 281-298 BibTeX
• Zheng Zhu, Steven D. Johnson: Automatic Synthesis of Sequential Synchronizations. 299-315 BibTeX

Session: Design Capture (short papers)

• Mohammed Faci, Luigi Logrippo: Specifying Hardware Systems in LOTOS. 319-326 BibTeX
• John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark Aagaard: HML: A Hardware Description Language Based on Standard ML. 327-334 BibTeX
• Bran Selic: An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems. 335-344 BibTeX
• Ahmed Amine Jerraya, Kevin O'Brien, Tarek Ben Ismail: Linking System Design Tools and Hardware Design Tools. 345-351 BibTeX
• Sungho Kang, Stephen A. Szygenda: Automatic VHDL Model Generation System. 353-360 BibTeX
• Balraj Singh, John Wicks, Philip Wright, James R. Armstrong: The Modeler's Assistant: A CAD Tool for Behavioral Model Development. 361-368 BibTeX
• Shailesh Sutarwala, Pierre G. Paulin, Yatish Kumar: Insulin: An Instruction Set Simulation Environment. 369-376 BibTeX
• Gregor von Bochmann: Specification Languages for Communication Protocols. 379-396 BibTeX

Session: Timing Specifications in HDLs

• Karim Khordoc, Mario Dufresne, Eduard Cerny, P. A. Babkine, Allan Silburt: Integrating Behavior and Timing in Executable Specifications. 399-416 BibTeX
• Tam Anh Chu, Huy T. Cao, Clement K. C. Leung: ESP: An Executable Specification Language for Mixed Timing Control Circuits. 417-434 BibTeX

Session: Textual and Graphical HDLs

• Tamio Hoshino: UDL/I version Two: A New Horizon of HDL Standards. 437-452 BibTeX
• Felice Balarin, Gary York: Verilog HDL Modeling Styles for Formal Verification. 453-465 BibTeX
• Eric J. Golin, Annette C. Feng: A Visual Hardware Description Language. 467-484 BibTeX
• Walling R. Cyre: Textual/Graphical Design Concept-Level Synthesis. 485-502 BibTeX

Session: VHDL

• Wolfgang Ecker, Sabine März: System-Level Specification and Design Using VHDL: A Case Study. 505-522 BibTeX
• Karen C. Davis: A Denotational Definition of the VHDL Simulation Kernel. 523-535 BibTeX
• Wolfgang Glunz, Torsten Rössel: Checking DFT Rules with a VHDL Simulator. 537-550 BibTeX
• Michael Ryba, Wolfram Seibold, Utz G. Baitinger, Ulrich Thelen: Parameterized VHDL Entities for the Simulation of Hybrid Circuits. 551-567 BibTeX
• Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai: Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. 569-586 BibTeX
• Dominique Rodriguez: Analog-VHDL: As an Application, a Real Example. 587-604 BibTeX