| 2007 |
|---|
| 7 | EE | Hiroe Iwasaki,
Jiro Naganuma,
Koyo Nitta,
Ken Nakamura,
Takeshi Yoshitome,
Mitsuo Ogura,
Yasuyuki Nakajima,
Yutaka Tashiro,
Takayuki Onishi,
Mitsuo Ikeda,
Toshihiro Minami,
Makoto Endo,
Yoshiyuki Yashima:
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.
IEEE Trans. VLSI Syst. 15(9): 1055-1059 (2007) |
| 2004 |
|---|
| 6 | | Ken Nakamura,
Takeshi Yoshitome,
Yoshiyuki Yashima:
Super high resolution video codec system with multiple MPEG-s HDTV codec LSI's.
ISCAS (3) 2004: 793-796 |
| 2003 |
|---|
| 5 | EE | Hiroe Iwasaki,
Jiro Naganuma,
Koyo Nitta,
Ken Nakamura,
Takeshi Yoshitome,
Mitsuo Ogura,
Yasuyuki Nakajima,
Yutaka Tashiro,
Takayuki Onishi,
Mitsuo Ikeda,
Makoto Endo:
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.
DATE 2003: 20002-20007 |
| 4 | | Takeshi Yoshitome,
Ken Nakamura,
Yoshiyuki Yashima,
Makoto Endo:
Scalable architecture for use in an over-HDTV real-time codec system for multiresolution video.
VCIP 2003: 1752-1759 |
| 2000 |
|---|
| 3 | EE | Ken Nakamura,
Mitsuo Ikeda,
Takeshi Yoshitome,
Takeshi Ogura:
Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System.
ITCC 2000: 195-200 |
| 1999 |
|---|
| 2 | EE | Mitsuo Ikeda,
Toshio Kondo,
Koyo Nitta,
Kazuhito Suguri,
Takeshi Yoshitome,
Toshihiro Minami,
Jiro Naganuma,
Takeshi Ogura:
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture.
DATE 1999: 44- |
| 1991 |
|---|
| 1 | | Takeshi Yoshitome:
Hierarchical Analyzer for VLSI Power Supply Networks Based on a New Reduction Method.
ICCAD 1991: 298-301 |
