| 2001 |
|---|
| 6 | EE | Tsukasa Yamauchi,
Shogo Nakaya,
Takeshi Inuo,
Nobuki Kajihara:
Arithmetic Operation Oriented Reconfigurable Chip: RHW.
FPL 2001: 618-622 |
| 2000 |
|---|
| 5 | EE | Tsukasa Yamauchi,
Shogo Nakaya,
Takeshi Inuo,
Nobuki Kajihara:
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW.
FCCM 2000: 281-282 |
| 1998 |
|---|
| 4 | | Hidenori Sakanashi,
Mehrdad Salami,
Masaya Iwata,
Shogo Nakaya,
Tsukasa Yamauchi,
Takeshi Inuo,
Nobuki Kajihara,
Tetsuya Higuchi:
Evolvable Hardware Chip for High Precision Printer Image Compression.
AAAI/IAAI 1998: 486-491 |
| 3 | EE | Isamu Kajitani,
Tsutomu Hoshino,
Daisuke Nishikawa,
Hiroshi Yokoi,
Shougo Nakaya,
Tsukasa Yamauchi,
Takeshi Inuo,
Nobuki Kajihara,
Masaya Iwata,
Didier Keymeulen,
Tetsuya Higuchi:
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI.
ICES 1998: 1-12 |
| 1996 |
|---|
| 2 | | Tsukasa Yamauchi,
Shogo Nakaya,
Nobuki Kajihara:
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method.
Parcella 1996: 128-136 |
| 1991 |
|---|
| 1 | | Tsukasa Yamauchi,
Akio Ishizuka,
Toshiyuki Nakata,
Nobuyuki Nishiguchi,
Nobuhiko Koike:
PROTON: A Parallel Detailed Router on an MIMD Parallel Machine.
ICCAD 1991: 340-343 |
