| 1997 |
|---|
| 6 | EE | Elizabeth M. Rudnick,
Janak H. Patel,
Gary S. Greenstein,
Thomas M. Niermann:
A genetic algorithm framework for test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1034-1044 (1997) |
| 1994 |
|---|
| 5 | EE | Elizabeth M. Rudnick,
Janak H. Patel,
Gary S. Greenstein,
Thomas M. Niermann:
Sequential Circuit Test Generation in a Genetic Algorithm Framework.
DAC 1994: 698-704 |
| 1992 |
|---|
| 4 | EE | Thomas M. Niermann,
Wu-Tung Cheng,
Janak H. Patel:
PROOFS: a fast, memory-efficient sequential circuit fault simulator.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 198-207 (1992) |
| 3 | EE | Thomas M. Niermann,
Rabindra K. Roy,
Janak H. Patel,
Jacob A. Abraham:
Test compaction for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 260-267 (1992) |
| 1991 |
|---|
| 2 | | Elizabeth M. Rudnick,
Thomas M. Niermann,
Janak H. Patel:
Methods for Reducing Events in Sequential Circuit Fault Simulation.
ICCAD 1991: 546-549 |
| 1990 |
|---|
| 1 | EE | Thomas M. Niermann,
Wu-Tung Cheng,
Janak H. Patel:
Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator.
DAC 1990: 535-540 |
