| |
| 1997 | ||
|---|---|---|
| 2 | EE | Glenn Holt, Akhilesh Tyagi: Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis. ISPD 1997: 48-53 |
| 1995 | ||
| 1 | EE | Glenn Holt, Akhilesh Tyagi: EPNR: an energy-efficient automated layout synthesis package. ICCD 1995: 224-229 |
| 1 | Akhilesh Tyagi | [1] [2] |