| 2007 |
|---|
| 11 | EE | Steven Wallace,
Kim M. Hazelwood:
SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance.
CGO 2007: 209-220 |
| 2005 |
|---|
| 10 | EE | Chi-Keung Luk,
Robert S. Cohn,
Robert Muth,
Harish Patil,
Artur Klauser,
P. Geoffrey Lowney,
Steven Wallace,
Vijay Janapa Reddi,
Kim M. Hazelwood:
Pin: building customized program analysis tools with dynamic instrumentation.
PLDI 2005: 190-200 |
| 2003 |
|---|
| 9 | EE | Cees de Laat,
Erik Radius,
Steven Wallace:
The rationale of the current optical networking initiatives.
Future Generation Comp. Syst. 19(6): 999-1008 (2003) |
| 2002 |
|---|
| 8 | EE | Joel S. Emer,
Pritpal Ahuja,
Eric Borch,
Artur Klauser,
Chi-Keung Luk,
Srilatha Manne,
Shubhendu S. Mukherjee,
Harish Patil,
Steven Wallace,
Nathan L. Binkert,
Roger Espasa,
Toni Juan:
Asim: A Performance Model Framework.
IEEE Computer 35(2): 68-76 (2002) |
| 1999 |
|---|
| 7 | EE | Steven Wallace,
Dean M. Tullsen,
Brad Calder:
Instruction Recycling on a Multiple-Path Processor.
HPCA 1999: 44-53 |
| 1998 |
|---|
| 6 | EE | Steven Wallace,
Brad Calder,
Dean M. Tullsen:
Threaded Multiple Path Execution.
ISCA 1998: 238-249 |
| 5 | EE | Steven Wallace,
Nader Bagherzadeh:
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.
IEEE Trans. Parallel Distrib. Syst. 9(6): 570-578 (1998) |
| 1997 |
|---|
| 4 | EE | Steven Wallace,
Nader Bagherzadeh:
Multiple Branch and Block Prediction.
HPCA 1997: 94- |
| 1996 |
|---|
| 3 | | Steven Wallace,
Nader Bagherzadeh:
Instruction Fetching Mechanisms for Superscalar Microprocessors.
Euro-Par, Vol. II 1996: 747-756 |
| 1995 |
|---|
| 2 | EE | Steven Wallace,
Nirav Dagli,
Nader Bagherzadeh:
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.
ICCD 1995: 96-101 |
| 1994 |
|---|
| 1 | | Steven Wallace,
Nader Bagherzadeh:
Performance Issues of a Superscalar Microprocessor.
ICPP (1) 1994: 293-297 |
