| 1999 |
|---|
| 6 | | Kisaburo Nakazawa,
Hiroshi Nakamura,
Taisuke Boku,
Ikuo Nakata,
Yoshiyuki Yamashita:
CP-PACS: A massively parallel processor at the University of Tsukuba.
Parallel Computing 25(13-14): 1635-1661 (1999) |
| 1997 |
|---|
| 5 | EE | Taisuke Boku,
Ken'ichi Itakura,
Hiroshi Nakamura,
Kisaburo Nakazawa:
CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations.
International Conference on Supercomputing 1997: 108-115 |
| 1995 |
|---|
| 4 | EE | Kotaro Shimamura,
Shigeya Tanaka,
Tetsuya Shimomura,
Takashi Hotta,
Eiki Kamada,
Hideo Sawamoto,
Teruhisa Shimizu,
Kisaburo Nakazawa:
A superscalar RISC processor with pseudo vector processing feature.
ICCD 1995: 102-109 |
| 1994 |
|---|
| 3 | | Hiroshi Nakamura,
Kisaburo Nakazawa,
Hang Li,
Hiromitsu Imori,
Taisuke Boku,
Ikuo Nakata,
Yoshiyuki Yamashita:
Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers.
HICSS (1) 1994: 368-377 |
| 1993 |
|---|
| 2 | EE | Hiroshi Nakamura,
Taisuke Boku,
Hideo Wada,
Hiromitsu Imori,
Ikuo Nakata,
Yasuhiro Inagami,
Kisaburo Nakazawa,
Yoshiyuki Yamashita:
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.
International Conference on Supercomputing 1993: 298-307 |
| 1992 |
|---|
| 1 | | Kisaburo Nakazawa,
Hiroshi Nakamura,
Hiromitsu Imori,
Shun Kawabe:
Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline.
SC 1992: 642-651 |
