1998 | ||
---|---|---|
2 | EE | Shoji Yoshida, Shigeya Tanaka, Kotaro Matsuo, Takashi Hotta, Hideo Sawamoto, Teruhisa Shimizu: Instruction fetch and dispatch scheme with flag-in-cache/in-IBR. Systems and Computers in Japan 29(4): 86-94 (1998) |
1995 | ||
1 | EE | Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa: A superscalar RISC processor with pseudo vector processing feature. ICCD 1995: 102-109 |
1 | Takashi Hotta | [1] [2] |
2 | Eiki Kamada | [1] |
3 | Kotaro Matsuo | [2] |
4 | Kisaburo Nakazawa | [1] |
5 | Hideo Sawamoto | [1] [2] |
6 | Kotaro Shimamura | [1] |
7 | Tetsuya Shimomura | [1] |
8 | Shigeya Tanaka | [1] [2] |
9 | Shoji Yoshida | [2] |