13. FCCM 2005:
Napa,
CA,
USA
13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings.
IEEE Computer Society 2005, ISBN 0-7695-2445-1 BibTeX
Introduction
Session 1:
Applications 1
Session 2:
Architecture
Session 3:
Tools 1
Session 4:
Graphics
Session 5:
Applications 2
- Martin Simka, Jan Pelzl, Thorsten Kleinjung, Jens Franke, Christine Priplata, Colin Stahlke, Milos Drutarovský, Viktor Fischer:
Hardware Factorization Based on Elliptic Curve Method.
107-116
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- Justin L. Tripp, Henning S. Mortveit, Anders A. Hansson, Maya Gokhale:
Metropolitan Road Traffic Simulation on FPGAs.
117-126
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- He Chuan, Wei Zhao, Mi Lu:
Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor Platform.
127-136
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Session 6:
Run Time
Session 7:
Arithmetic
Session 8:
Device Architecture
Session 9:
Networking
Session 10:
Tools 2
Posters
- M. Y. Niamat, Surya S. Hejeebu, M. Alam:
A BIST Approach for Testing FPGAs Using JBITS.
267-268
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- Yongfeng Gu, Tom Van Court, Douglas DiSabello, Martin C. Herbordt:
Preliminary Report: FPGA Acceleration of Molecular Dynamics Computations.
269-270
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- David Fang, John Teifel, Rajit Manohar:
A High-Performance Asynchronous FPGA: Test Results.
271-272
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- Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt:
Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures.
273-274
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- Robert McIlhenny, Milos D. Ercegovac:
RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions.
275-276
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- John A. Williams, Neil W. Bergmann, X. Xie:
FIFO Communication Models in Operating Systems for Reconfigurable Computing.
277-278
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- Naohito Nakasato, Tsuyoshi Hamada:
Astrophysical Hydrodynamics Simulations on a Reconfigurable System.
279-280
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- Matthew French, Li Wang, Tyler Anderson, Michael J. Wirthlin:
Post Synthesis Level Power Modeling of FPGAs.
281-282
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- Daewook Kim, Manho Kim, Gerald E. Sobelman:
FPGA-Based CDMA Switch for Networks-on-Chip.
283-284
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- Shakith Fernando, Yajun Ha:
Design of Networked Reconfigurable Encryption Engine.
285-286
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- Brian Greskamp, Ron Sass:
A Virtual Machine for Merit-Based Runtime Reconfiguration.
287-288
Electronic Edition (link) BibTeX
- Mark Holland, Scott Hauck:
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC.
289-290
Electronic Edition (link) BibTeX
- Xin Jia, Ranga Vemuri:
The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture.
291-292
Electronic Edition (link) BibTeX
- Joshua M. Lucas, Raymond Hoare, Alex K. Jones:
Optimizing Technology Mapping for FPGAs Using CAMs.
293-294
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- H. Sofikitis, K. Roumpou, Apostolos Dollas, Nikolaos G. Bourbakis:
An Architecture for Video Compression Based on the SCAN Algorithm.
295-296
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- Apostolos Dollas, Ioannis Ermis, Iosif Koidis, Ioannis Zisis, Christopher Kachris:
An Open TCP/IP Core for Reconfigurable Logic.
297-298
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- Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely:
Mutable Codesign for Embedded Protocol Processing.
299-300
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- Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis:
Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems.
301-302
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- Andrea Lodi, Luca Ciccarelli, Claudio Mucci, Roberto Giansante, Andrea Cappelli, Mario Toma:
An Embedded Reconfigurable Datapath for SoC.
303-304
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- J. Greg Nash:
Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs.
305-306
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- Mayumi Kato, Chia-Tien Dan Lo:
Hardware Solution to Java Compressed Heap.
307-308
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- Petersen F. Curt, James P. Durbano, Fernando E. Ortiz, John R. Humphrey, Dennis W. Prather:
A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms.
309-310
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- Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi:
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA.
311-314
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- Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki:
Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor.
315-316
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- Jing Ma, Xin-Ming Huang:
A System-on-Programmable Chip Approach for MIMO Sphere Decoder.
317-318
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- Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.
319-320
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- Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto:
Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms.
321-322
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- Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna:
High-Performance FPGA-Based General Reduction Methods.
323-324
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- Jasmine Lam, John McAllister, Jennifer Dudley:
Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs.
325-326
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- Luis E. Cordova, Duncan A. Buell, Sreesa Akella:
The DARPA Dynamic Programming Benchmark on a Reconfigurable Computer.
327-328
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- Tsuyoshi Hamada, Naohito Nakasato:
Massively Parallel Processors Generator for Reconfigurable System.
329-330
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- Muhammad Z. Hasan, Sotirios G. Ziavras:
FPGA-Based Vector Processing for Solving Sparse Sets of Equations.
331-332
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- Joseph Zambreno, Daniel Honbo, Alok N. Choudhary:
Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures.
333-334
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- Apostolos Dollas, Dionissios Efstathiou, Georgios Vernardos, Elias Polytarchos, Konstantinos Kazakos:
On Distributed Reconfigurable Systems: Open Problems and Some Initial Solutions.
335-336
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Copyright © Sat May 16 23:11:55 2009
by Michael Ley (ley@uni-trier.de)
