| |
| 2001 | ||
|---|---|---|
| 3 | EE | Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri: Verification of Basic Block Schedules Using RTL Transformations. CHARME 2001: 173-178 |
| 2 | EE | Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri: On the verification of synthesized designs using automatically generated transformational witnesses. DATE 2001: 798 |
| 1 | Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri: Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. Formal Methods in System Design 19(3): 237-273 (2001) | |
| 1 | Sriram Govindarajan | [1] |
| 2 | Naren Narasimhan | [1] |
| 3 | Rajesh Radhakrishnan | [1] [2] [3] |
| 4 | Ranga Vemuri | [1] [2] [3] |