Volume 39,
Number 1,
September 2005
Volume 39,
Number 2,
March 2006
Low-power design techniques
- Kaushik Roy:
Guest Editorial.
63
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- Bipul Chandra Paul, Amit Agarwal, Kaushik Roy:
Low-power design techniques for scaled technologies.
64-89
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- Jia Di, Jiann S. Yuan, Ronald F. DeMara:
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
90-112
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- David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris:
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems.
113-130
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- Matthias Müller, Sven Simon, Holger Gryska, Andreas Wortmann, Steffen Buch:
Low power synthesizable register files for processor and IP cores.
131-155
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Volume 39,
Number 3,
June 2006
- Jihyun Lee, Yong-Bin Kim:
ASLIC: A low power CMOS analog circuit design automation.
157-181
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- Victor R. L. Shen:
A PN-based approach to the high-level synthesis of digital systems.
182-204
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- J. Tong, X. Zou, X. B. Shen:
Simulation for a novel vertical SOI configuration.
205-210
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- Mohamed Raseen, P. W. Chandana Prasad, Ali Assi:
An efficient estimation of the ROBDD's complexity.
211-228
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- Nabil Abu-Khader, Pepe Siy:
Systolic Galois field exponentiation in a multiple-valued logic technique.
229-251
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- Rezaul Haque, Andrzej Sendrowski, Bob Baltar, Saad Monasa:
Design of a high-speed, low-noise CMOS data output buffer.
252-266
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- Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri:
Hierarchical constraint transformation based on genetic optimization for analog system synthesis.
267-290
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- Joanna C. K. Lai, Waleed H. Abdulla, Stephan Hussmann:
Hardware implementation of a sub-pixel algorithm for real-time saw blade deflection monitoring.
291-309
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Volume 39,
Number 4,
July 2006
- Lei Yang, C.-J. Richard Shi:
FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits.
311-339
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- Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia:
On whitespace and stability in physical synthesis.
340-362
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- Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilzadeh:
A parameterized graph-based framework for high-level test synthesis.
363-381
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- Donald B. Shaw, Dhamin Al-Khalili, Come Rozon:
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries.
382-406
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- Anu Gupta, Bipin Kulkarni:
Automation of clock distribution network design for digital integrated circuits using divide and conquer technique.
407-419
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- Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen:
Multilevel routing with jumper insertion for antenna avoidance.
420-432
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- S. Engels, Robin Wilson, Nadine Azémard, Philippe Maurine:
A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects.
433-456
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- Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu:
A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design.
457-473
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- Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu:
Erratum to: "High-speed systolic architectures for finite field inversion" [Integration 38(3) (2005) 383-398].
474-476
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Copyright © Sun May 17 00:03:49 2009
by Michael Ley (ley@uni-trier.de)
