6. FCCM 1998:
Napa,
CA,
USA
6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA.
IEEE Computer Society 1998, ISBN 0-8186-8900-5 BibTeX
@proceedings{DBLP:conf/fccm/1998,
title = {6th IEEE Symposium on Field-Programmable Custom Computing Machines
(FCCM '98), 15-17 April 1998, Napa Valley, CA, USA},
booktitle = {FCCM},
publisher = {IEEE Computer Society},
year = {1998},
isbn = {0-8186-8900-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Architectures I
Special Purpose Systems
Architectures II
Applications I
Compilers
Tools for Run Time Reconfiguration
Module Generation
Applications II
Arithmetic
Applications III
Poster Session 1
- Philip Heng Wai Leong, P. K. Tsang, T. K. Lee:
A FPGA Based Forth Microprocessor.
254-255
Electronic Edition (link) BibTeX
- Tsuyoshi Hamada, Toshiyuki Fukushige, Atsushi Kawai, Joshiyuki Makino:
PROGRAPE-1: A Programmable Special-Purpose Computer for Many-Body Simulations.
256-257
Electronic Edition (link) BibTeX
- José Carlos Alves, José Silva Matos:
RVC - A Reconfigurable Coprocessor for Vector Processing Applications.
258-259
Electronic Edition (link) BibTeX
- I. M. Bland, Graham M. Megson:
The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology.
260-261
Electronic Edition (link) BibTeX
- Andreas Kugel, Klaus Kornmesser, R. Lay, J. Ludvig, Reinhard Männer, K. H. Noffz, Stephan Rühl, M. Sessler, Harald Simmler, Holger Singpiel:
50 kHz Pattern Recognition on the Large FPGA Processor Enable++.
262-
Electronic Edition (link) BibTeX
- Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina:
An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration.
264-266
Electronic Edition (link) BibTeX
- Jeffrey M. Arnold:
Mapping the MD5 Hash Algorithm onto the NAPA Architecture.
267-268
Electronic Edition (link) BibTeX
- Apostolos Dollas, Euripides Sotiriades, Apostolos Emmanouelides, Lee House:
General Purpose vs. Custom FCCM's: a Comparison of Splash2, Quickturn RPM, and GE1 for Golomb Ruler Derivation.
269-270
Electronic Edition (link) BibTeX
- Jeffrey M. Arnold:
An Architecture Simulator for National Semiconductor's Adaptive Processing Architecture (NAPA).
271-272
Electronic Edition (link) BibTeX
- S. Kumar, Luiz Pires, D. Pandalai, M. Vojta, J. Golusky, S. Wadi, Henk A. E. Spaanenburg:
Benchmarking Technology for Configurable Computing System.
273-274
Electronic Edition (link) BibTeX
- M. F. Sakr, Steven P. Levitan, C. Lee Giles, Donald M. Chiarulli:
Reconfigurable Processor Architectures Exploiting High Bandwidth Optical Channels.
275-
Electronic Edition (link) BibTeX
Poster Session 2
- André Stauffer, Moshe Sipper, Andrés Pérez-Uribe:
Some Applications of FPGAs in Bio-Inspired Hardware.
278-279
Electronic Edition (link) BibTeX
- João Canas Ferreira, José Silva Matos:
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware.
280-281
Electronic Edition (link) BibTeX
- Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohen, Brian Bray:
Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application.
282-283
Electronic Edition (link) BibTeX
- T. K. Lee, Philip Heng Wai Leong, K. H. Lee, K. T. Chan, S. K. Hui, H. K. Yeung, M. F. Lo, J. H. M. Lee:
An FPGA Implementation of GENET for Solving Graph Coloring Problems .
284-285
Electronic Edition (link) BibTeX
- Stephen P. Crago, Brian Schott, Robert Parker:
SLAAC: A Distributed Architecture for Adaptive Computing.
286-287
Electronic Edition (link) BibTeX
- Jacques-Olivier Haenni, Jean-Luc Beuchat, Eduardo Sanchez:
RENCO: A Reconfigurable Network Computer.
288-289
Electronic Edition (link) BibTeX
- Emeka Mosanya, Jean-Michel Puiatti, Eduardo Sanchez:
Hardware Implementation of Generalized Profile Search on the GENSTORM Machine.
290-291
Electronic Edition (link) BibTeX
- Hagen Ploog, Dirk Timmermann:
FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards.
292-293
Electronic Edition (link) BibTeX
- Matthew Moe, Herman Schmit, Seth Copen Goldstein:
Characterization and Parameterization of a Pipeline Reconfigurable FPGA.
294-
Electronic Edition (link) BibTeX
Poster Session 3
- Donald L. Hung, Jun Wang:
A FPGA-Based Custom Computing System for Solving the Assignment Problem.
298-299
Electronic Edition (link) BibTeX
- Gordon J. Brebner:
Circlets: Circuits as Applets.
300-301
Electronic Edition (link) BibTeX
- Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah:
Dynamic Reconfiguration to Support Concurrent Applications.
302-303
Electronic Edition (link) BibTeX
- Pascal Poiré, Marc-André Cantin, Hervé Daniel, Yves Blaquière, Yvon Savaria:
A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing.
304-305
Electronic Edition (link) BibTeX
- Paul Graham, Brent E. Nelson:
Frequency-Domain Sonar Processing in FPGAs and DSPs.
306-307
Electronic Edition (link) BibTeX
- Nicholas McKay, Thomas F. Melham, Kong Woei Susanto, Satnam Singh:
Dynamic Specialization of XC6200 FPGAs by Partial Evaluation.
308-309
Electronic Edition (link) BibTeX
- Tom Kean, Ann Duncan:
DES Key Breaking, Encryption and Decryption on the XC6216.
310-311
Electronic Edition (link) BibTeX
- Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri:
An Effective Design System for Dynamically Reconfigurable Architectures.
312-313
Electronic Edition (link) BibTeX
- Andreas Dandalis, Viktor K. Prasanna:
Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures.
314-
Electronic Edition (link) BibTeX
Poster Session 4
- Sakir Sezer, Roger Woods, Jean-Paul Heron, Alan Marshall:
Fast Partial Reconfiguration for FCCMs.
318-319
Electronic Edition (link) BibTeX
- Gunter Haug, Wolfgang Rosenstiel:
Reconfigurable Hardware as Shared Resource for Parallel Threads.
320-321
Electronic Edition (link) BibTeX
- Hanho Lee, Gerald E. Sobelman:
Digit-Serial DSP Library for Optimized FPGA Configuration.
322-323
Electronic Edition (link) BibTeX
- Pedro Merino, Margarida F. Jacome, Juan Carlos López:
A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems.
324-325
Electronic Edition (link) BibTeX
- Goran Doncev, Miriam Leeser, Shantanu Tarafdar:
High Level Synthesis for Designing Custom Computing Hardware.
326-328
Electronic Edition (link) BibTeX
- Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Temporal Partitioning and Scheduling for Reconfigurable Computing.
329-330
Electronic Edition (link) BibTeX
- Luiz Maltar, Felipe M. G. França, Vladimir Castro Alves, Cláudio L. Amorim:
Implementation of RNS Addition and RNS Multiplication into FPGAs.
331-332
Electronic Edition (link) BibTeX
- Al Walters, Peter Athanas:
A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine.
333-334
Electronic Edition (link) BibTeX
- Nikhil D. Gupta, John K. Antonio, Jack M. West:
Reconfigurable Computing for Space-Time Adaptive Processing.
335-336
Electronic Edition (link) BibTeX
- Manoucher Shaditalab, Guy Bois, Mohamad Sawan:
Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks.
337-338
Electronic Edition (link) BibTeX
- Donald Soderman, Yuri Panchul:
Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog.
339-
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:11:54 2009
by Michael Ley (ley@uni-trier.de)
