CASES 2000: San Jose, California, USA

• Amir Pnueli:
  Rigorous development of embedded systems. 1
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• Daniel Weil, Valérie Bertin, Etienne Closse, Michel Poize, Patrick Venier, Jacques Pulou:
  Efficient compilation of ESTEREL for real-time embedded systems. 2-8
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• Fridtjof Siebert:
  Eliminating external fragmentation in a non-moving garbage collector for Java. 9-17
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• Jeff Tsay, Christopher Hylands, Edward Lee:
  A code generation framework for Java component-based designs. 18-25
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• Jürgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert:
  A joined architecture/compiler design environment for ASIPs. 26-33
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• Koen Danckaert, Francky Catthoor, Hugo De Man:
  A preprocessing step for global loop transformations for data transfer optimization. 34-40
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• Michel Barreteau, Juliette Mattioli, Thierry Grandpierre, Christophe Lavarenne, Yves Sorel, Philippe Bonnot, Philippe Kajfasz:
  PROMPT: a mapping environment for telecom applications on "system-on-a-chip". 41-47
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• Antti Takko, Marko Hännikäinen, Jarno Knuutila, Timo Hämäläinen, Jukka Saarinen:
  Embedding SDL implemented protocols into DSP. 48-56
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• Timothy J. Callahan, John Wawrzynek:
  Adapting software pipelining for reconfigurable computing. 57-64
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• Randall S. Janka, Linda M. Wills:
  Specification and synthesis of real-time embedded distributed and parallel multiprocessor-based signal processing systems. 65-70
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• Santosh G. Abraham, B. Ramakrishna Rau:
  Efficient design space exploration in PICO. 71-79
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• Prashant Arora, Rajesh K. Gupta:
  Design and implementation of a hierarchical exception handling extension to systemC. 80-84
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• Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
  Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. 85-93
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• Benoît Dupont de Dinechin, François de Ferrière, Christophe Guillon, Artour Stoutchinin:
  Code generator optimizations for the ST120 DSP-MCU core. 93-102
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• Peng Yang, Dirk Desmet, Francky Catthoor, Diederik Verkest:
  Dynamic scheduling of concurrent tasks with cost performance trade-off. 103-109
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• Shige Wang, Kang G. Shin:
  An architecture for embedded software integration using reusable components. 110-118
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• B. Ramakrishna Rau:
  The era of embedded computing. 119
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• Hsien-Hsin S. Lee, Gary S. Tyson:
  Region-based caching: an energy-delay efficient memory architecture for embedded processors. 120-127
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• Tor M. Aamodt, Paul Chow:
  Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. 128-137
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• Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Energy-oriented compiler optimizations for partitioned memory architectures. 138-147
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• Yonghong Song, Yuan Lin:
  Unroll-and-jam for imperfectly-nested loops in DSP applications. 148-156
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• Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik:
  Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. 157-164
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• Afzal Malik, Bill Moyer, Dan Cermak:
  A programmable unified cache architecture for embedded applications. 165-171
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• Michael J. Schulte, Pablo I. Balzola, Jie Ruan, C. John Glossner:
  Parallel saturating multioperand adders. 172-179
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• Mohamed Shalan, Vincent John Mooney III:
  A dynamic memory management unit for embedded real-time system-on-a-chip. 180-186
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• Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky:
  A first-step towards an architecture tuning methodology for low power. 187-192
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• Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung:
  Flexible instruction processors. 193-200
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