| 2001 |
|---|
| 4 | EE | Jianbang Lai,
Ming-Shiun Lin,
Ting-Chi Wang,
Li-C. Wang:
Module placement with boundary constraints using the sequence-pair representation.
ASP-DAC 2001: 515-520 |
| 3 | EE | Zhi-Hong Wang,
En-Cheng Liu,
Jianbang Lai,
Ting-Chi Wang:
Power minization in LUT-based FPGA technology mapping.
ASP-DAC 2001: 635-640 |
| 2 | EE | Yi-He Jiang,
Jianbang Lai,
Ting-Chi Wang:
Module placement with pre-placed modules using the B*-tree representation.
ISCAS (5) 2001: 347-350 |
| 1 | EE | En-Cheng Liu,
Ming-Shiun Lin,
Jianbang Lai,
Ting-Chi Wang:
Slicing floorplan design with boundary-constrained modules.
ISPD 2001: 124-129 |
