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Jianbang Lai

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2001
4EEJianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang: Module placement with boundary constraints using the sequence-pair representation. ASP-DAC 2001: 515-520
3EEZhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang: Power minization in LUT-based FPGA technology mapping. ASP-DAC 2001: 635-640
2EEYi-He Jiang, Jianbang Lai, Ting-Chi Wang: Module placement with pre-placed modules using the B*-tree representation. ISCAS (5) 2001: 347-350
1EEEn-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang: Slicing floorplan design with boundary-constrained modules. ISPD 2001: 124-129

Coauthor Index

1Yi-He Jiang [2]
2Ming-Shiun Lin [1] [4]
3En-Cheng Liu [1] [3]
4Li-C. Wang [4]
5Ting-Chi Wang [1] [2] [3] [4]
6Zhi-Hong Wang [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)