DFT 1994:
Montréal,
Quebec,
Canada
The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 17-19, 1994, Montréal, Quebec, Canada, Proceedings.
IEEE Computer Society 1994, ISBN 0-8186-6307-3 BibTeX
@proceedings{DBLP:conf/dft/1994,
title = {The IEEE International Workshop on Defect and Fault Tolerance
in VLSI Systems, October 17-19, 1994, Montr{\'e}al, Quebec,
Canada, Proceedings},
booktitle = {DFT},
publisher = {IEEE Computer Society},
year = {1994},
isbn = {0-8186-6307-3},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Fault Tolerant Architectures
Testable Architectures
Yield and Defect Model
Invited Speaker
Self-Checking and Coding Techniques
- Fabio Salice, Mariagiovanna Sami, Donatella Sciuto:
Synthesis of Multi-level Self-Checking Logic.
115-123 BibTeX
- T. Bogue, Helmut Jürgensen, Michael Gössel:
Design of Cover Circuits for Monitoring the Output of a MISA.
124-132 BibTeX
- Cecilia Metra, Michele Favalli, Bruno Riccò:
CMOS Self Checking Circuits with Faulty Sequential Functional Block.
133-141 BibTeX
- Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly Testable and Compact 1-out-of-n CMOS Checkers.
142-150 BibTeX
- Sihai Xiao, Xiaofa Shi, Guilang Feng, T. R. N. Rao:
Some Results on Improving the Code Length of SbEC-DED Codes.
151-158 BibTeX
Fault-Tolerant Techniques
Reconfiguration Techniques
Yield Enhancement
Testing Techniques
Copyright © Sat May 16 23:06:34 2009
by Michael Ley (ley@uni-trier.de)
