Vijay Raghunat

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2006

1 EE Yan Lin, Yu Hu, Lei He, Vijay Raghunat: An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED 2006: 168-173

2006
1	EE	Yan Lin, Yu Hu, Lei He, Vijay Raghunat: An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED 2006: 168-173

Coauthor Index

1 Lei He [1]

2 Yu Hu [1]

3 Yan Lin [1]