9. SLIP 2007: Austin, Texas, USA

Andrew A. Kennings, Ion I. Mandoiu (Eds.): The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings. ACM 2007, ISBN 978-1-59593-622-6 BibTeX

Wire-length and layout sensitivity prediction

Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu:
Adaptable wire-length distribution with tunable occupation probability. 1-8
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Payman Zarkesh-Ha, Ken Doniger:
Stochastic interconnect layout sensitivity model. 9-14
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Congestion estimation

Taraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh:
Tutorial on congestion prediction. 15-24
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Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma:
An accurate and efficient probabilistic congestion estimation model in x architecture. 25-32
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David Yeager, Darius Chiu, Guy G. Lemieux:
Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. 33-40
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Process variation

Alexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang:
Principle hessian direction based parameter reduction for interconnect networks with process variation. 41-46
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I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang:
Statistical circuit optimization considering device andinterconnect process variations. 47-54
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Advanced interconnect architectures

Avinoam Kolodny:
Networks on chips: keeping up with Rent's rule and Moore's law. 55-56
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Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli:
Early wire characterization for predictable network-on-chip global interconnects. 57-64
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Wim Heirman, Joni Dambre, Jan Van Campenhout:
Synthetic traffic generation as a tool for dynamic interconnect evaluation. 65-72
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Interconnect technology evaluation

Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand:
Impact of interconnect length changes on effective materials properties (dielectric constant). 73-80
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Hoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, Krishna Saraswat:
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects. 81-88
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Physical synthesis and on-chip delay optimization

Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. 89-94
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Yu Hu, King Ho Tam, Tong Jing, Lei He:
Fast dual-vdd buffering based on interconnect prediction and sampling. 95-102
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Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu:
Exploiting on-chip data behavior for delay minimization. 103-110
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