| 2009 |
|---|
| 9 | EE | Guillermo Payá Vayá,
Javier Martín-Langerwerf,
Sören Moch,
Peter Pirsch:
An Enhanced DMA Controller in SIMD Processors for Video Applications.
ARCS 2009: 159-170 |
| 2005 |
|---|
| 8 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Sören Moch,
Lars Friebe,
Mark Bernd Kulaczewski,
Sebastian Flügel,
Heiko Klußmann,
Andreas Dehnhardt,
Peter Pirsch:
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing.
VLSI Signal Processing 41(1): 9-20 (2005) |
| 2004 |
|---|
| 7 | EE | Sören Moch,
Mladen Berekovic,
Hans-Joachim Stolberg,
Lars Friebe,
Mark Bernd Kulaczewski,
Andreas Dehnhardt,
Peter Pirsch:
HIBRID-SOC: a multi-core architecture for image and video applications.
SIGARCH Computer Architecture News 32(3): 55-61 (2004) |
| 6 | EE | Mladen Berekovic,
Sören Moch,
Peter Pirsch:
A scalable, clustered SMT processor for digital signal processing.
SIGARCH Computer Architecture News 32(3): 62-69 (2004) |
| 2003 |
|---|
| 5 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Sebastian Flügel,
Xun Mao,
Mark Bernd Kulaczewski,
Heiko Klußmann,
Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications.
DATE 2003: 20008-20013 |
| 4 | | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Sebastian Flügel,
Mark Bernd Kulaczewski,
Peter Pirsch:
HiBRID-SoC: a multi-core architecture for image and video applications.
ICIP (3) 2003: 101-104 |
| 3 | | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Mark Bernd Kulaczewski,
Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing.
VLSI-SOC 2003: 155-160 |
| 2002 |
|---|
| 2 | EE | Markus Rudack,
Michael Redeker,
Jörg Hilgenstock,
Sören Moch,
Jens Castagne:
A Large-Area Integrated Multiprocessor System for Video Applications.
IEEE Design & Test of Computers 19(1): 6-17 (2002) |
| 2000 |
|---|
| 1 | EE | Klaus Herrmann,
Sören Moch,
Jörg Hilgenstock,
Peter Pirsch:
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit.
DFT 2000: 105-113 |
