| 2008 |
|---|
| 12 | EE | Adam Golda,
Andrzej Kos:
Neural Processor as a Dynamic Power Manager for Digital Systems.
MICAI 2008: 333-342 |
| 11 | EE | Ireneusz Brzozowski,
Andrzej Kos:
A new approach to power estimation and reduction in CMOS digital circuits.
Integration 41(2): 219-237 (2008) |
| 10 | EE | Slawomir Mikula,
Gilbert De Mey,
Andrzej Kos:
Asynchronous control of modules activity in integrated systems for reducing peak temperatures.
Integration 41(3): 447-458 (2008) |
| 2007 |
|---|
| 9 | | Ireneusz Brzozowski,
Andrzej Kos:
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation.
DDECS 2007: 139-144 |
| 2005 |
|---|
| 8 | EE | Ireneusz Brzozowski,
Andrzej Kos:
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.
PATMOS 2005: 456-465 |
| 2004 |
|---|
| 7 | EE | Adam Golda,
Andrzej Kos:
Temperature influence on energy losses in MOSFET capacitors.
Microelectronics Reliability 44(7): 1115-1121 (2004) |
| 2003 |
|---|
| 6 | EE | Adam Golda,
Andrzej Kos:
Temperature Influence on Power Consumption and Time Delay.
DSD 2003: 378-383 |
| 5 | | Adam Golda,
Andrzej Kos:
Static Versus Dynamic Power Losses in CMOS VLSI Systems Considering Temperature.
VLSI-SOC 2003: 252-257 |
| 2001 |
|---|
| 4 | EE | Piotr Bratek,
Andrzej Kos:
A method of thermal testing of microsystems.
Microelectronics Reliability 41(11): 1877-1887 (2001) |
| 3 | EE | Piotr Dziurdzia,
Andrzej Kos:
Monitoring of power dissipated in microelectronic structures.
Microelectronics Reliability 41(12): 1971-1978 (2001) |
| 1999 |
|---|
| 2 | EE | Ireneusz Brzozowski,
Andrzej Kos:
Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching Activity.
EUROMICRO 1999: 1376- |
| 1993 |
|---|
| 1 | | Andrzej Kos:
An approach to thermal placement in power electronics using neural networks.
ISCAS 1993: 2427-2430 |
