2006 |
10 | EE | Dimitris Bakalis,
K. Adaos,
D. Lymperopoulos,
Maciej Bellos,
Haridimos T. Vergos,
George Alexiou,
Dimitris Nikolos:
A core generator for arithmetic cores and testing structures with a network interface.
Journal of Systems Architecture 52(1): 1-12 (2006) |
2005 |
9 | EE | Maciej Bellos,
Dimitris Nikolos:
Deterministic Test Vector Compression / Decompression Using an Embedded Processor.
EDCC 2005: 318-331 |
2004 |
8 | EE | Maciej Bellos,
Dimitris Bakalis,
Dimitris Nikolos,
Xrysovalantis Kavousianos:
Low Power Testing by Test Vector Ordering with Vector Repetition.
ISQED 2004: 205-210 |
7 | EE | Maciej Bellos,
Dimitris Bakalis,
Dimitris Nikolos:
Scan Cell Ordering for Low Power BIST.
ISVLSI 2004: 281-284 |
6 | EE | Xrysovalantis Kavousianos,
Dimitris Bakalis,
Maciej Bellos,
Dimitris Nikolos:
An Efficient Test Vector Ordering Method for Low Power Testing.
ISVLSI 2004: 285-288 |
2003 |
5 | EE | Maciej Bellos,
Dimitri Kagaris,
Dimitris Nikolos:
Low Power Test Set Embedding Based on Phase Shifters.
ISVLSI 2003: 155-160 |
4 | | Maciej Bellos,
Xrysovalantis Kavousianos,
Dimitris Nikolos,
Dimitri Kagaris:
DV-TSE: Difference Vector Based Test Set Embedding.
VLSI-SOC 2003: 343- |
3 | EE | Haridimos T. Vergos,
Dimitris Nikolos,
Maciej Bellos,
Costas Efstathiou:
Deterministic BIST for RNS Adders.
IEEE Trans. Computers 52(7): 896-906 (2003) |
2002 |
2 | EE | Maciej Bellos,
Dimitrios Kagaris,
Dimitris Nikolos:
Test Set Embedding Based on Phase Shifters.
EDCC 2002: 90-101 |
1999 |
1 | EE | Maciej Bellos,
Dimitris Nikolos,
Haridimos T. Vergos:
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks.
EDCC 1999: 267-282 |