| 2006 |
|---|
| 10 | EE | Raúl Jiménez,
Pilar Parra,
Javier Castro,
Manuel Sánchez,
Antonio J. Acosta:
Optimization of Master-Slave Flip-Flops for High-Performance Applications.
PATMOS 2006: 439-449 |
| 9 | EE | Fermín Dalmagro,
Juan Jiménez,
Raúl Jiménez,
Haydée Lugo:
Bounded-rational-prisoners' dilemma: On critical phenomena of cooperation.
Applied Mathematics and Computation 176(2): 462-469 (2006) |
| 2005 |
|---|
| 8 | EE | Francisco de Toro,
Raúl Jiménez,
Manuel Sánchez,
Julio Ortega:
Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms.
PATMOS 2005: 629-637 |
| 7 | EE | Pilar Parra,
Antonio J. Acosta,
Raúl Jiménez,
Manuel Valencia:
Selective Clock-Gating for Low-Power Synchronous Counters.
J. Low Power Electronics 1(1): 11-19 (2005) |
| 2003 |
|---|
| 6 | EE | Raúl Jiménez,
Pilar Parra,
Pedro Sanmartín,
Antonio J. Acosta:
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application.
PATMOS 2003: 491-500 |
| 2002 |
|---|
| 5 | EE | Raúl Jiménez,
Pilar Parra,
Pedro Sanmartín,
Antonio J. Acosta:
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.
PATMOS 2002: 209-218 |
| 2001 |
|---|
| 4 | EE | José M. Quintana,
Maria J. Avedillo,
Raúl Jiménez,
Esther Rodríguez-Villegas:
Practical low-cost CPL implementations threshold logic functions.
ACM Great Lakes Symposium on VLSI 2001: 139-144 |
| 2000 |
|---|
| 3 | EE | Raúl Jiménez,
Antonio J. Acosta,
Eduardo J. Peralías,
Adoración Rueda:
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.
PATMOS 2000: 295-305 |
| 2 | EE | Antonio J. Acosta,
Raúl Jiménez,
Jorge Juan-Chico,
Manuel J. Bellido,
Manuel Valencia:
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.
PATMOS 2000: 316-326 |
| 1995 |
|---|
| 1 | EE | Antonio J. Acosta,
Manuel J. Bellido,
Manuel Valencia,
Angel Barriga Barrios,
Raúl Jiménez,
José L. Huertas:
New CMOS VLSI linear self-timed architectures.
ASYNC 1995: 14-23 |
