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Abbas Sheibanyrad

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2008
4EEAbbas Sheibanyrad, Alain Greiner: Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures. Integration 41(1): 17-26 (2008)
2007
3EEAbbas Sheibanyrad, Ivan Miro Panades, Alain Greiner: Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. DATE 2007: 1090-1095
2 Abbas Sheibanyrad, Alain Greiner: Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures. ESA 2007: 27-33
2006
1EEAbbas Sheibanyrad, Alain Greiner: Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. PATMOS 2006: 191-202

Coauthor Index

1Alain Greiner [1] [2] [3] [4]
2Ivan Miro Panades [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)