| 2007 |
|---|
| 7 | EE | Javier Castro,
Pilar Parra,
Manuel Valencia,
Antonio J. Acosta:
Asymmetric clock driver for improved power and noise performances.
ISCAS 2007: 893-896 |
| 2006 |
|---|
| 6 | EE | Pilar Parra,
A. Viana,
O. Rodríguez,
M. Knoblauch,
F. Alcojor,
S. Sánchez,
J. Ignacio García,
O. García,
Daniel Meziat:
EDROOM, Herramienta Libre de Modelado y Generación Automática de Código para Sistemas de Tiempo Real.
DSDM 2006 |
| 5 | EE | Raúl Jiménez,
Pilar Parra,
Javier Castro,
Manuel Sánchez,
Antonio J. Acosta:
Optimization of Master-Slave Flip-Flops for High-Performance Applications.
PATMOS 2006: 439-449 |
| 2005 |
|---|
| 4 | EE | Pilar Parra,
Antonio J. Acosta,
Raúl Jiménez,
Manuel Valencia:
Selective Clock-Gating for Low-Power Synchronous Counters.
J. Low Power Electronics 1(1): 11-19 (2005) |
| 2003 |
|---|
| 3 | EE | Raúl Jiménez,
Pilar Parra,
Pedro Sanmartín,
Antonio J. Acosta:
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application.
PATMOS 2003: 491-500 |
| 2002 |
|---|
| 2 | EE | Raúl Jiménez,
Pilar Parra,
Pedro Sanmartín,
Antonio J. Acosta:
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.
PATMOS 2002: 209-218 |
| 1 | EE | Pilar Parra,
Antonio J. Acosta,
Manuel Valencia:
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.
PATMOS 2002: 448-457 |
