2008 |
28 | EE | José L. Risco-Martín,
José Ignacio Hidalgo,
Juan Lanchares,
Oscar Garnica:
Solving discrete deceptive problems with EMMRS.
GECCO 2008: 1139-1140 |
27 | EE | José Ignacio Hidalgo,
José L. Risco-Martín,
David Atienza,
Juan Lanchares:
Analysis of multi-objective evolutionary algorithms to optimize dynamic data types in embedded systems.
GECCO 2008: 1515-1522 |
26 | EE | Pablo Fernández-Blanco,
Diego J. Bodas-Sagi,
Francisco J. Soltero,
José Ignacio Hidalgo:
Technical market indicators optimization using evolutionary algorithms.
GECCO (Companion) 2008: 1851-1858 |
25 | EE | José Manuel Colmenar,
Noelia Morón,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo:
Modelling Asynchronous Systems using Probability Distribution Functions.
PDP 2008: 3-11 |
24 | EE | José L. Risco-Martín,
David Atienza,
José Ignacio Hidalgo,
Juan Lanchares:
A parallel evolutionary algorithm to optimize dynamic data types in embedded systems.
Soft Comput. 12(12): 1157-1167 (2008) |
2007 |
23 | EE | José Ignacio Hidalgo,
Francisco Fernández de Vega,
Juan Lanchares,
Daniel Lombraña Gonzalez:
Is the island model fault tolerant?
GECCO 2007: 1519 |
22 | EE | José Ignacio Hidalgo,
Juan Lanchares,
Francisco Fernández de Vega,
Daniel Lombraña Gonzalez:
Is the island model fault tolerant?
GECCO (Companion) 2007: 2737-2744 |
21 | EE | David Atienza,
Christos Baloukas,
Lazaros Papadopoulos,
Christophe Poucet,
Stylianos Mamagkakis,
José Ignacio Hidalgo,
Francky Catthoor,
Dimitrios Soudris,
Juan Lanchares:
Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation.
SCOPES 2007: 31-40 |
2006 |
20 | EE | José Manuel Colmenar,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo,
Guadalupe Miñana,
Sonia López:
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.
DSD 2006: 423-432 |
19 | EE | Guadalupe Miñana,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
José Manuel Colmenar:
A Power-Aware Technique for Functional Units in High-Performance Processors.
DSD 2006: 456-459 |
18 | EE | José Manuel Colmenar,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo,
Guadalupe Miñana,
Sonia López:
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.
Euro-Par 2006: 495-505 |
17 | EE | Guadalupe Miñana,
José Ignacio Hidalgo,
Oscar Garnica,
Juan Lanchares,
José Manuel Colmenar,
Sonia López:
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.
PATMOS 2006: 514-523 |
2005 |
16 | EE | José Ignacio Hidalgo,
Francisco Fernández:
Balancing the computation effort in genetic algorithms.
Congress on Evolutionary Computation 2005: 1645-1652 |
15 | EE | Guadalupe Miñana,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
José Manuel Colmenar:
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.
PATMOS 2005: 40-48 |
2004 |
14 | EE | José Manuel Colmenar,
Oscar Garnica,
Sonia López,
José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays.
PDP 2004: 112-119 |
13 | EE | Francisco Fernández,
José Ignacio Hidalgo,
Juan Lanchares,
J. M. Sánchez:
A methodology for reconfigurable hardware design based upon evolutionary computation.
Microprocessors and Microsystems 28(7): 363-371 (2004) |
2003 |
12 | EE | José Ignacio Hidalgo,
Francisco Fernández de Vega,
Juan Lanchares,
Juan Manuel Sánchez-Pérez,
Román Hermida,
Marco Tomassini,
Ranieri Baraglia,
Raffaele Perego,
Oscar Garnica:
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation.
GECCO 2003: 2109-2120 |
11 | EE | Sonia López,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.
PATMOS 2003: 151-160 |
10 | EE | José Ignacio Hidalgo,
Manuel Prieto,
Juan Lanchares,
Ranieri Baraglia,
Francisco Tirado,
Oscar Garnica:
Hybrid Parallelization of a Compact Genetic Algorithm.
PDP 2003: 449-455 |
2002 |
9 | EE | Aitor Ibarra,
José M. Mendías,
Juan Lanchares,
José Ignacio Hidalgo,
Román Hermida:
Optimization of Equational Specifications Using Genetic Techniques.
DSD 2002: 252-258 |
8 | EE | José Ignacio Hidalgo,
Juan Lanchares,
Aitor Ibarra,
Román Hermida:
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design.
DSD 2002: 60-69 |
7 | EE | Aitor Ibarra,
Juan Lanchares,
Jose Manuel Mendias,
José Ignacio Hidalgo,
Román Hermida:
Transformation of Equational Specification by Means of Genetic Programming.
EuroGP 2002: 248-257 |
2001 |
6 | EE | Aitor Ibarra,
Juan Lanchares,
José Ignacio Hidalgo,
F. Saenz:
Pipelined Genetic Architecture with Fitness on the Fly.
DSD 2001: 382-385 |
5 | EE | Ranieri Baraglia,
José Ignacio Hidalgo,
Raffaele Perego:
A Parallel Hybrid Heuristic for the TSP.
EvoWorkshops 2001: 193-202 |
4 | | Ranieri Baraglia,
José Ignacio Hidalgo,
Raffaele Perego:
A hybrid heuristic for the traveling salesman problem.
IEEE Trans. Evolutionary Computation 5(6): 613-622 (2001) |
2000 |
3 | EE | José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms.
EUROMICRO 2000: 1204-1211 |
1999 |
2 | EE | José Ignacio Hidalgo,
Manuel Prieto,
Juan Lanchares,
Francisco Tirado,
B. de Andrés,
S. Esteban,
D. Rivera:
A Method for Model Parameter Identification Using Parallel Genetic Algorithms.
PVM/MPI 1999: 291-298 |
1997 |
1 | EE | José Ignacio Hidalgo,
Juan Lanchares:
Functional Partitioning for Hardware-Software Codesign using Genetic Algorithms.
EUROMICRO 1997: 631-638 |